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Full-Text Articles in Nanoscience and Nanotechnology
Vertical Carbon Nanotube Devices With Nanoscale Lengths Controlled Without Lithography, Aaron D. Franklin, Robert A. Sayer, Timothy D. Sands, David B. Janes, Timothy S. Fisher
Vertical Carbon Nanotube Devices With Nanoscale Lengths Controlled Without Lithography, Aaron D. Franklin, Robert A. Sayer, Timothy D. Sands, David B. Janes, Timothy S. Fisher
PRISM: NNSA Center for Prediction of Reliability, Integrity and Survivability of Microsystems
Vertical single-walled carbon nanotubes (vSWCNTs) are synthesized within highly ordered porous anodic alumina (PAA) templates supported on Si substrates. A process for obtaining thin-film PAA with long-range ordered nanopores is presented in this paper. Each nanopore contains at most one v-SWCNT that is supported by a dielectric and addressed by electrochemically formed Pd nanowire source contacts and evaporated Pd drain contacts. Characteristics of these completely vertical, two-terminal nanotube devices are presented. Control of the v-SWCNT length is demonstrated using a straightforward etching process with lengths of less than 100 nm achieved without the need for complex/expensive lithography. This effective nanoscale …
Toward Surround Gates On Vertical Single-Walled Carbon Nanotube Devices, Aaron D. Franklin, Robert A. Sayer, Timothy D. Sands, Timothy S. Fisher, David B. Janes
Toward Surround Gates On Vertical Single-Walled Carbon Nanotube Devices, Aaron D. Franklin, Robert A. Sayer, Timothy D. Sands, Timothy S. Fisher, David B. Janes
PRISM: NNSA Center for Prediction of Reliability, Integrity and Survivability of Microsystems
The one-dimensional, cylindrical nature of single-walled carbon nanotubes (SWCNTs) suggests that the ideal gating geometry for nanotube field-effect transistors (FETs) is a surround gate (SG). Using vertical SWCNTs templated in porous anodic alumina, SGs are formed using top-down processes for the dielectric/metal depositions and definition of the channel length. Surround gates allow aggressive scaling of the channel to 25% of the length attainable with a bottom-gate geometry without incurring short-channel effects. The process demonstrated here for forming SGs on vertical SWCNTs is amenable for large-scale fabrication of multinanotube FETs.