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Articles 1 - 3 of 3
Full-Text Articles in Nanoscience and Nanotechnology
Fabrication, Characterization And Simulation Of Non-Lithographic Nanostructures And Their Potential Applications, Neelanjan Bhattacharya
Fabrication, Characterization And Simulation Of Non-Lithographic Nanostructures And Their Potential Applications, Neelanjan Bhattacharya
UNLV Theses, Dissertations, Professional Papers, and Capstones
The dissertation describes the formation of porous silicon through the pores of porous alumina on a silicon substrate. Porous silicon, by itself, is inherently a non-uniform material that has non-uniform optical and electronic properties. In addition, it is also mechanically fragile material requiring careful material handling. The porous silicon fabricated through the nanosized pores of porous alumina are expected to mitigate these problems, thereby enhancing commercial viability of the device. The porous silicon as well the porous alumina have been synthesized through anodisation for various parameters and also various types of anodizing electrolytes. The porous silicon, so obtained have been …
The Applications And Limitations Of Printable Batteries, Matthew Delmanowski
The Applications And Limitations Of Printable Batteries, Matthew Delmanowski
Graphic Communication
This study focuses on the potential applications for printed batteries and how they could affect the printing industry. It also analyzes the main problems associated with manufacturing this technology and what needs to be done to overcome these issues. To find the answers to these questions, two methods of research were used. The first was through the elite and specialized interviewing of Dr. Scott Williams of Rochester Institute of Technology and Professor Nancy Cullins from Cal Poly. The second form of research was a common, yet useful, method called secondary research. This entailed looking at recent written research papers about …
Nano-Scaled Fet Device For Cmos Technology, Prabhat Ranjan Pathak
Nano-Scaled Fet Device For Cmos Technology, Prabhat Ranjan Pathak
Dissertations
In this work the 3-D structure of the Accumulation mode (ACM) and Enhance mode (ECM) FinFET was developed by the Taurus-Device Editor. The design of both ACM and ECM FinFET was optimized for high-performance IC applications to meet ITRS specification for Ioff current, for 9nm gate length. The design of ACM and ECM FinFET is optimized, analyzed and compared against each other with respect to Darin Induced Barrier Lower (DIBL), Sub-threshold Swing(SS), operation and performance characteristics with varying electrical and physical parameters Silicon thickness (Tsi), Source/Drain doping gradient (σsd), electrical channel length (Leff ), …