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Articles 1 - 6 of 6
Full-Text Articles in Nanoscience and Nanotechnology
Cause And Prevention Of Moisture-Induced Degradation Of Resistance Random Access Memory Nanodevices, Albert Chen
Cause And Prevention Of Moisture-Induced Degradation Of Resistance Random Access Memory Nanodevices, Albert Chen
Albert B Chen
Dielectric thin films in nanodevices may absorb moisture, leading to physical changes and property/performance degradation, such as altered data storage and readout in resistance random access memory. Here we demonstrate using a nanometallic memory that such degradation proceeds via nanoporosity, which facilitates water wetting in otherwise nonwetting dielectrics. Electric degradation only occurs when the device is in the charge-storage state, which provides a nanoscale dielectrophoretic force directing H2O to internal field centers (sites of trapped charge) to enable bond rupture and charged hydroxyl formation. While these processes are dramatically enhanced by an external DC or AC field and electron-donating electrodes, …
Demonstration And Modeling Of Multi-Bit Resistance Random Access Memory, Albert Chen
Demonstration And Modeling Of Multi-Bit Resistance Random Access Memory, Albert Chen
Albert B Chen
Although intermediates resistance states are common in resistance random access memory (RRAM), two-way switching among them has not been demonstrated. Using a nanometallic bipolar RRAM, we have illustrated a general scheme for writing/rewriting multi-bit memory using voltage pulses. Stability conditions for accessing intermediate states have also been determined in terms of a state distribution function and the weight of serial load resistance. A multi-bit memory is shown to realize considerable space saving at a modest decrease of switching speed.
Analysis Of Scratches Formed On Oxide Surface During Chemical Mechanical Planarization, Jae-Gon Choi, Y. Prasad, In-Kwon Kim, In-Gon Kim, Woo-Jin Kim, Ahmed Busnaina, Jin-Goo Park
Analysis Of Scratches Formed On Oxide Surface During Chemical Mechanical Planarization, Jae-Gon Choi, Y. Prasad, In-Kwon Kim, In-Gon Kim, Woo-Jin Kim, Ahmed Busnaina, Jin-Goo Park
Jin-Goo Park
Scratch formation on patterned oxide wafers during the chemical mechanical planarization process was investigated. Silica and ceria slurries were used for polishing the experiments to observe the effect of abrasives on the scratch formation. Interlevel dielectric patterned wafers were used to study the scratch dimensions, and shallow trench isolation patterned wafers were used to study the effect of polishing parameters, such as pressure and rotational speed (head/platen). Similar shapes of scratches (chatter type) were observed with both types of slurries. The length of the scratch formed might be related to the period of contact between the wafer and the pad. …
Purely Electronic Switching With High Uniformity, Resistance Tunability, And Good Retention In Pt-Dispersed Sio2 Thin Films For Reram, Albert Chen
Albert B Chen
Resistance switching memory operating by a purely electronic switching mechanism, which was first realized in Pt-dispersed SiO2 thin films, satisfies criteria including high uniformity, fast switching speed, and long retention for non-volatile memory application. This resistive element obeys Ohm's law for the area dependence, but its resistance exponentially increases with the film thickness, which provides new freedom to tailor the device characteristics.
Direct Measurement Of Graphene Adhesion On Silicon Surface By Intercalation Of Nanoparticles, Zong Zong, Chia-Ling Chen, Mehmet Dokmeci, Kai-Tak Wan
Direct Measurement Of Graphene Adhesion On Silicon Surface By Intercalation Of Nanoparticles, Zong Zong, Chia-Ling Chen, Mehmet Dokmeci, Kai-Tak Wan
Mehmet R. Dokmeci
We report a technique to characterize adhesion of monolayered/multilayered graphene sheets on silicon wafer. Nanoparticles trapped at graphene-silicon interface act as point wedges to support axisymmetric blisters. Local adhesion strength is found by measuring the particle height and blister radius using a scanning electron microscope. Adhesion energy of the typical graphene-silicon interface is measured to be 151±28 mJ/m2. The proposed method and our measurements provide insights in fabrication and reliability of microelectromechanical/nanoelectromechanical systems.
Low-Voltage And Short-Channel Pentacene Field-Effect Transistors With Top-Contact Geometry Using Parylene-C Shadow Masks, Yoonyoung Chung, Boris Murmann, Selvapraba Selvarasah, Mehmet Dokmeci, Zhenan Bao
Low-Voltage And Short-Channel Pentacene Field-Effect Transistors With Top-Contact Geometry Using Parylene-C Shadow Masks, Yoonyoung Chung, Boris Murmann, Selvapraba Selvarasah, Mehmet Dokmeci, Zhenan Bao
Mehmet R. Dokmeci
We have fabricated high-performance top-contact pentacene field-effect transistors using a nanometer-scale gate dielectric and parylene-C shadow masks. The high-capacitance gate dielectric, deposited by atomic layer deposition of aluminum oxide, resulted in a low operating voltage of 2.5 V. The flexible and conformal parylene-C shadow masks allowed fabrication of transistors with channel lengths of L = 5, 10, and 20 μm. The field-effect mobility of the transistors was μ = 1.14 (±0.08) cm²/V s on average, and the IMAX/IMIN ratio was greater than 10⁶.