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California Polytechnic State University, San Luis Obispo
Operations Research, Systems Engineering and Industrial Engineering
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Full-Text Articles in Mechanical Engineering
Board Level Failure Analysis Of Chip Scale Package Drop Test Assemblies, Nicholas Vickers, Kyle Rauen, Andrew Farris, Jianbiao Pan
Board Level Failure Analysis Of Chip Scale Package Drop Test Assemblies, Nicholas Vickers, Kyle Rauen, Andrew Farris, Jianbiao Pan
Industrial and Manufacturing Engineering
This paper presents the failure analysis results of board level drop tests. In this study, the test vehicle was designed according to the requirements of the Joint Electron Device Engineering Council (JEDEC) drop test board. The test vehicle was assembled with 15 chip scale packages (CSPs) each having 228 daisy-chained 0.5 mm pitch solder joints using Sn-3.0 wt% Ag-0.5 wt% Cu (SAC305) lead free solder. Assemblies were drop tested using three different peak accelerations of 900 G, 1500 G, 2900 G, with 0.7 ms, 0.5 ms, and 0.3 ms pulse durations, respectively. Scanning electron microscopy (SEM) with energy dispersive spectroscopy …