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Articles 1 - 30 of 103
Full-Text Articles in VLSI and Circuits, Embedded and Hardware Systems
General Design Procedure For Free And Open-Source Hardware For Scientific Equipment, Shane W. Oberloier, Joshua M. Pearce
General Design Procedure For Free And Open-Source Hardware For Scientific Equipment, Shane W. Oberloier, Joshua M. Pearce
Joshua M. Pearce
Distributed digital manufacturing of free and open-source scientific hardware (FOSH) used for scientific experiments has been shown to in general reduce the costs of scientific hardware by 90–99%. In part due to these cost savings, the manufacturing of scientific equipment is beginning to move away from a central paradigm of purchasing proprietary equipment to one in which scientists themselves download open-source designs, fabricate components with digital manufacturing technology, and then assemble the equipment themselves. This trend introduces a need for new formal design procedures that designers can follow when targeting this scientific audience. This study provides five steps in the …
Randomized Routing On Fat-Trees, Ronald I. Greenberg, Charles E. Leiserson
Randomized Routing On Fat-Trees, Ronald I. Greenberg, Charles E. Leiserson
Ronald Greenberg
Fat-trees are a class of routing networks for hardware-efficient parallel computation. This paper presents a randomized algorithm for routing messages on a fat-tree. The quality of the algorithm is measured in terms of the load factor of a set of messages to be routed, which is a lower bound on the time required to deliver the messages. We show that if a set of messages has load factor lambda on a fat-tree with n processors, the number of delivery cycles (routing attempts) that the algorithm requires is O(lambda + lg n lg lg n) with probability 1-O(1/n). The best previous …
The Fat-Pyramid And Universal Parallel Computation Independent Of Wire Delay, Ronald I. Greenberg
The Fat-Pyramid And Universal Parallel Computation Independent Of Wire Delay, Ronald I. Greenberg
Ronald Greenberg
This paper shows that a fat-pyramid of area Θ(A) requires only O(log A) slowdown to simulate any competing network of area A under very general conditions. The result holds regardless of the processor size (amount of attached memory) and number of processors in the competing networks as long as the limitation on total area is met. Furthermore, the result is valid regardless of the relationship between wire length and wire delay. We especially focus on elimination of the common simplifying assumption that unit time suffices to traverse a wire regardless of its length, since the assumption becomes more and more …
Randomized Routing On Fat-Trees, Ronald I. Greenberg
Randomized Routing On Fat-Trees, Ronald I. Greenberg
Ronald Greenberg
Fat-trees are a class of routing networks for hardware-efficient parallel computation. This paper presents a randomized algorithm for routing messages on a fat-tree. The quality of the algorithm is measured in terms of the load factor of a set of messages to be routed, which is a lower bound on the time required to deliver the messages. We show that if a set of messages has load factor lambda on a fat-tree with n processors, the number of delivery cycles (routing attempts) that the algorithm requires is O(lambda+lgnlglgn) with probability 1-O(1/ …
Universal Wormhole Routing, Ronald I. Greenberg, Hyeong-Cheol Oh
Universal Wormhole Routing, Ronald I. Greenberg, Hyeong-Cheol Oh
Ronald Greenberg
In this paper, we examine the wormhole routing problem in terms of the “congestion” c and “dilation” d for a set of packet paths. We show, with mild restrictions, that there is a simple randomized algorithm for routing any set of P packets in O(cdη+cLηlogP) time with high probability, where L is the number of flits in a packet, and η=min{d,L}; only a constant number of flits are stored in each queue at any time. Using this result, we show that a fat-tree network of area Θ(A) can simulate wormhole routing on any network of comparable area with O(log^3 A) …
Single-Layer Channel Routing And Placement With Single-Sided Nets, Ronald I. Greenberg, Jau-Der Shih
Single-Layer Channel Routing And Placement With Single-Sided Nets, Ronald I. Greenberg, Jau-Der Shih
Ronald Greenberg
This paper considers the optimal offset, feasible offset, and optimal placement problems for a more general form of single-layer VLSI channel routing than has usually been considered in the past. Most prior works require that every net has exactly one terminal on each side of the channel. As long as only one side of the channel contains multiple terminals of the same net, we provide linear-time solutions to all three problems. Such results are implausible if the placement of terminals is entirely unrestricted; in fact, the size of the output for the feasible offset problem may be Ω(n^2). The linear-time …
On The Difficulty Of Manhattan Channel Routing, Ronald I. Greenberg, Joseph Jaja, Sridhar Krishnamurthy
On The Difficulty Of Manhattan Channel Routing, Ronald I. Greenberg, Joseph Jaja, Sridhar Krishnamurthy
Ronald Greenberg
We show that channel routing in the Manhattan model remains difficult even when all nets are single-sided. Given a set of n single-sided nets, we consider the problem of determining the minimum number of tracks required to obtain a dogleg-free routing. In addition to showing that the decision version of the problem isNP-complete, we show that there are problems requiring at least d+Omega(sqrt(n)) tracks, where d is the density. This existential lower bound does not follow from any of the known lower bounds in the literature.
On The Area Of Hypercube Layouts, Ronald I. Greenberg, Lee Guan
On The Area Of Hypercube Layouts, Ronald I. Greenberg, Lee Guan
Ronald Greenberg
This paper precisely analyzes the wire density and required area in standard styles for the hypercube. It shows that the most natural, regular layout of a hypercube of N^2 nodes in the plane, in a NxN grid arrangement, uses floor(2N/3)+1 horizontal wiring tracks for each row of nodes. (In the process, we see that the number of tracks per row can be reduced by 1 with a less regular design, as can also be seen from an independent argument of Bezrukov et al.) This paper also gives a simple formula for the wire density at any cut position and a …
Minimum Separation For Single-Layer Channel Routing, Ronald I. Greenberg, F. Miller Maley
Minimum Separation For Single-Layer Channel Routing, Ronald I. Greenberg, F. Miller Maley
Ronald Greenberg
We present a linear-time algorithm for determining the minimum height of a single-layer routing channel. The algorithm handles single-sided connections and multiterminal nets. It yields a simple routability test for single-layer switchboxes, correcting an error in the literature.
Mulch: A Multi-Layer Channel Router Using One, Two, And Three Layer Partitions, Ronald I. Greenberg, Alex T. Ishii, Alberto L. Sangiovanni-Vincentelli
Mulch: A Multi-Layer Channel Router Using One, Two, And Three Layer Partitions, Ronald I. Greenberg, Alex T. Ishii, Alberto L. Sangiovanni-Vincentelli
Ronald Greenberg
Chameleon, a channel router for three layers of interconnect, has been implemented to accept specification of an arbitrary number of layers. Chameleon is based on a strategy of decomposing the multilayer problem into two- and three-layer problems in which one of the layers is reserved primarily for vertical wire runs and the other layer(s) for horizontal runs. In some situations, however, it is advantageous to consider also layers that allow the routing of entire nets, using both horizontal and vertical wires. MulCh is a multilayer channel router that extends the algorithms of Chameleon in this direction. MulCh can route channels …
Minimizing Channel Density With Movable Terminals, Ronald I. Greenberg, Jau-Der Shih
Minimizing Channel Density With Movable Terminals, Ronald I. Greenberg, Jau-Der Shih
Ronald Greenberg
We give algorithms to minimize density for channels with terminals that are movable subject to certain constraints. The main cases considered are channels with linear order constraints, channels with linear order constraints and separation constraints, channels with movable modules containing fixed terminals, and channels with movable modules and terminals. In each case, previous results for running time and space are improved by a factor of L/lg n and L , respectively, where L is the channel length and n is the number of terminals.
Minimizing Channel Density With Movable Terminals, Ronald I. Greenberg, Jau-Der Shih
Minimizing Channel Density With Movable Terminals, Ronald I. Greenberg, Jau-Der Shih
Ronald Greenberg
We give algorithms to minimize density for VLSI channel routing problems with terminals that are movable subject to certain constraints. The main cases considered are channels with linear order constraints, channels with linear order constraints and separation constraints, channels with movable modules containing fixed terminals, and channels with movable modules and terminals. In each case, we improve previous results for running time and space by a factor of L/\lgn and L, respectively, where L is the channel length, and n is the number of terminals.
Parallel Algorithms For Single-Layer Channel Routing, Ronald I. Greenberg, Shih-Chuan Hung, Jau-Der Shih
Parallel Algorithms For Single-Layer Channel Routing, Ronald I. Greenberg, Shih-Chuan Hung, Jau-Der Shih
Ronald Greenberg
We provide efficient parallel algorithms for the minimum separation, offset range, and optimal offset problems for single-layer channel routing. We consider all the variations of these problems that have linear-time sequential solutions rather than limiting attention to the ``river-routing'' context, where single-sided connections are disallowed. For the minimum separation problem, we obtain O(lgN) time on a CREW PRAM or O(lgN/lglgN) time on a CRCW PRAM, both with optimal work (processor-time product) of O(N), where N is the number of terminals. For the offset range problem, we obtain the same time and processor bounds as long as only one side of …
Parallel Algorithms For Single-Layer Channel Routing, Ronald I. Greenberg, Shih-Chuan Hung, Jau-Der Shih
Parallel Algorithms For Single-Layer Channel Routing, Ronald I. Greenberg, Shih-Chuan Hung, Jau-Der Shih
Ronald Greenberg
We provide efficient parallel algorithms for the minimum separation, offset range, and optimal offset problems for single-layer channel routing. We consider all the variations of these problems that are known to have linear- time sequential solutions rather than limiting attention to the "river-routing" context, where single-sided connections are disallowed. For the minimum separation problem, we obtain O(lgN) time on a CREW PRAM or O(lgN / lglgN) time on a (common) CRCW PRAM, both with optimal work (processor- time product) of O(N), where N is the number of terminals. For the offset range problem, we obtain the same time and processor …
Feasible Offset And Optimal Offset For Single-Layer Channel Routing, Ronald I. Greenberg, Jau-Der Shih
Feasible Offset And Optimal Offset For Single-Layer Channel Routing, Ronald I. Greenberg, Jau-Der Shih
Ronald Greenberg
The paper provides an efficient method to find all feasible offsets for a given separation in a VLSI channel routing problem in one layer. The prior literature considers this task only for problems with no single-sided nets. When single-sided nets are included, the worst-case solution time increases from Theta(n) to Omega(n^2), where n is the number of nets. But, if the number of columns c is O(n), one can solve the problem in time O(n^{1.5}lg n ), which improves upon a `naive' O(cn) approach. As a corollary of this result, the same time bound suffices to find the optimal offset …
Lower Bounds On The Area Of Finite-State Machines, M. J. Foster, Ronald I. Greenberg
Lower Bounds On The Area Of Finite-State Machines, M. J. Foster, Ronald I. Greenberg
Ronald Greenberg
There are certain straightforward algorithms for laying out finite-state machines. This paper shows that these algorithm are optimal in the worst case for machines with fixed alphabets. That is, for any s and k, there is a deterministic finite-state machine with s states and k symbols such that any layout algorithm requires Ω(ks log s) area to lay out its realization. Similarly, any layout algorithm requires Ω(ks^2) area in the worst case for nondeterministic finite-state machines with s states and k symbols.
Efficient Multi-Layer Channel Routing, Ronald I. Greenberg
Efficient Multi-Layer Channel Routing, Ronald I. Greenberg
Ronald Greenberg
No abstract provided.
Finding A Maximum-Denisty Planar Subset Of A Set Of Nets In A Channel, Ronald I. Greenberg, Jau-Der Shih
Finding A Maximum-Denisty Planar Subset Of A Set Of Nets In A Channel, Ronald I. Greenberg, Jau-Der Shih
Ronald Greenberg
We present efficient algorithms to find a maximum-density planar subset of n 2-pin nets in a channel. The simplest approach is to make repeated usage of Supowit's dynamic programming algorithm for finding a maximum-size planar subset, which leads to O(n^3) time to find a maximum-density planar subset. But we also provide an algorithm whose running time is dependent on other problem parameters and is often more efficient. A simple bound on the running time of this algorithm is O(nlgn+n(t+1)w), where t is the number of two-sided nets, and w is the number of nets in the output. Though the worst-case …
Efficient Interconnection Schemes For Vlsi And Parallel Computation, Ronald I. Greenberg
Efficient Interconnection Schemes For Vlsi And Parallel Computation, Ronald I. Greenberg
Ronald Greenberg
This thesis is primarily concerned with two problems of interconnecting components in VLSI technologies. In the first case, the goal is to construct efficient interconnection networks for general-purpose parallel computers. The second problem is a more specialized problem in the design of VLSI chips, namely multilayer channel routing. In addition, a final part of this thesis provides lower bounds on the area required for VLSI implementations of finite-state machines. This thesis shows that networks based on Leiserson's fat-tree architecture are nearly as good as any network built in a comparable amount of physical space. It shows that these "universal" networks …
An Empirical Comparison Of Area-Universal And Other Parallel Computing Networks, Ronald I. Greenberg, Lee Guan
An Empirical Comparison Of Area-Universal And Other Parallel Computing Networks, Ronald I. Greenberg, Lee Guan
Ronald Greenberg
This paper provides empirical comparison of the communication capabilities of two area-universal networks, the fat-tree and the fat-pyramid, to the popular mesh and hypercube networks for parallel computation. While area-universal networks have been proven capable of simulating, with modest slowdown, any computation of any other network of comparable area, prior work has generally left open the question of how area-universal networks compare to other networks in practice. Comparisons are performed using techniques of throughput and latency analysis that have previously been applied to k-ary n-cube networks and using various existing models to equate the hardware cost of the networks being …
A Systolic Simulation And Transformation System, Ronald I. Greenberg, H.-C. Oh
A Systolic Simulation And Transformation System, Ronald I. Greenberg, H.-C. Oh
Ronald Greenberg
This paper presents a CAD tool, SystSim, to ease the design of systolic systems. Given a high-level, functional description of processors, and a high-level description of their interconnection, SystSim will perform simulations and provide graphical output. SystSim will also perform transformations such as retiming, which eases use of the methodology of Leiserson and Saxe of designing a system with broadcasting and then obtaining a systolic system through retiming.
Data And Network Optimization Effect On Web Performance, Steven Rosenberg, Surbhi Dangi, Isuru Warnakulasooriya
Data And Network Optimization Effect On Web Performance, Steven Rosenberg, Surbhi Dangi, Isuru Warnakulasooriya
Surbhi Dangi
In this study, we measure the effects of two software approaches to improving data and network performance: 1. Content optimization and compression; and 2. Optimizing network protocols. We achieve content optimization and compression by means of BoostEdge by ActivNetworks and employ the SPDY network protocol by Google to lower the round trip time for HTTP transactions. Since the data and transport layers are separate, we conclude our investigation by studying the combined effect of these two techniques on web performance. Using document mean load time as the measure, we found that with and without packet loss, both BoostEdge and SPDY …
From Verification To Implementation: A Model Translation Tool And A Pacemaker Case Study, Miroslav Pajic, Zhihao Jiang, Insup Lee, Oleg Sokolsky, Rahul Mangharam
From Verification To Implementation: A Model Translation Tool And A Pacemaker Case Study, Miroslav Pajic, Zhihao Jiang, Insup Lee, Oleg Sokolsky, Rahul Mangharam
Oleg Sokolsky
Model-Driven Design (MDD) of cyber-physical systems advocates for design procedures that start with formal modeling of the real-time system, followed by the model’s verification at an early stage. The verified model must then be translated to a more detailed model for simulation-based testing and finally translated into executable code in a physical implementation. As later stages build on the same core model, it is essential that models used earlier in the pipeline are valid approximations of the more detailed models developed downstream. The focus of this effort is on the design and development of a model translation tool, UPP2SF, and …
Brief Comparison Between 8051 And Avr, Ata Jahangir Moshayedi
Brief Comparison Between 8051 And Avr, Ata Jahangir Moshayedi
Ata Jahangir Moshayedi
Brief comparison between 8051 and AVR
Wireless Transmission Network : A Imagine, Radhey Shyam Meena Engineer, Neeraj Kumar Garg Asst.Prof
Wireless Transmission Network : A Imagine, Radhey Shyam Meena Engineer, Neeraj Kumar Garg Asst.Prof
Radhey Shyam Meena
World cannot be imagined without electrical power. Generally the power is transmitted through transmission networks. This paper describes an original idea to eradicate the hazardous usage of electrical wires which involve lot of confusion in particularly organizing them. Imagine a future in which wireless power transfer is feasible: cell phones, household robots, mp3 players, laptop computers and other portable electronic devices capable of charging themselves without ever being plugged in freeing us from that final ubiquitous power wire. This paper includes the techniques of transmitting power without using wires with an efficiency of about 95% with non-radioactivemethods. In this paper …
Battery Energy Storage System In Solar Power Generation, Radhey Shyam Meena Er., Deepa Sharma
Battery Energy Storage System In Solar Power Generation, Radhey Shyam Meena Er., Deepa Sharma
Radhey Shyam Meena
Grid-connected solar PV dramatically changes the load profile of an electric utility customer. The expected widespread adoption of solar generation by customers on the distribution system poses significant challenges to system operators both in transient and steady state operation, from issues including voltage swings, sudden weather-induced changes in generation, and legacy protective devices designed with one-way power flow in mind
Battery Energy Storage System In Solar Power Generation, Radhey Shyam Meena Er.
Battery Energy Storage System In Solar Power Generation, Radhey Shyam Meena Er.
Radhey Shyam Meena
As solar photovoltaic power generation becomes more commonplace, the inherent intermittency of the solar resource poses one of the great challenges to those who would design and implement the next generation smart grid. Specifically, grid-tied solar power generation is a distributed resource whose output can change extremely rapidly, resulting in many issues for the distribution system operator with a large quantity of installed photovoltaic devices. Battery energy storage systems are increasingly being used to help integrate solar power into the grid. These systems are capable of absorbing and delivering both real and reactive power with sub-second response times. With these …
At The Tone, The Time Will Be... Unknown – A Perspective On The Evolution Of Time In Telecommunications, Robert Iannucci
At The Tone, The Time Will Be... Unknown – A Perspective On The Evolution Of Time In Telecommunications, Robert Iannucci
Robert A Iannucci
No abstract provided.
A Simple Low-Voltage Cascode Current Mirror With Enhanced Dynamic Performance, Bradley Minch
A Simple Low-Voltage Cascode Current Mirror With Enhanced Dynamic Performance, Bradley Minch
Bradley Minch
In this paper, we present a simple low-voltage MOS cascode current mirror featuring a step response and an output voltage swing comparable to those of a simple mirror and and output resistance comparable to that of a stacked mirror. The proposed mirror operates with an input voltage of Vdiode+VDSsat and can operate on a minimum supply of Vdiode + 2VDSsat. We validate the proposed mirror with a combination of simulated and measured results from a circuit prototyped from transistor arrays fabricated in a 0.5-μm CMOS process through MOSIS.
From Verification To Implementation: A Model Translation Tool And A Pacemaker Case Study, Miroslav Pajic, Zhihao Jiang, Insup Lee, Oleg Sokolsky, Rahul Mangharam
From Verification To Implementation: A Model Translation Tool And A Pacemaker Case Study, Miroslav Pajic, Zhihao Jiang, Insup Lee, Oleg Sokolsky, Rahul Mangharam
Rahul Mangharam
Model-Driven Design (MDD) of cyber-physical systems advocates for design procedures that start with formal modeling of the real-time system, followed by the model’s verification at an early stage. The verified model must then be translated to a more detailed model for simulation-based testing and finally translated into executable code in a physical implementation. As later stages build on the same core model, it is essential that models used earlier in the pipeline are valid approximations of the more detailed models developed downstream. The focus of this effort is on the design and development of a model translation tool, UPP2SF, and …