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Articles 1 - 16 of 16
Full-Text Articles in Signal Processing
Universal Computer Aided Design For Electrical Machines, Aravind Cv, Grace I, Rozita Teymourzadeh, Rajkumar R, Raj R, Wong Yv
Universal Computer Aided Design For Electrical Machines, Aravind Cv, Grace I, Rozita Teymourzadeh, Rajkumar R, Raj R, Wong Yv
Dr. Rozita Teymourzadeh, CEng.
Electrical machines are devices that change either mechanical or electrical energy to the other and also can alternate the voltage levels of an alternating current. The need for electrical machines cannot be overemphasized since they are used in various applications in the world today. Its design is to meet the specifications as stated by the user and this design has to be an economical one. The design therefore revolves around designing the machine to meet the stipulated performance required, the cost available and the lasting life of the machine. This work aims to eliminate the tediousness involved in the manual …
Fpga Implementation Of Pipeline Digit-Slicing Multiplier-Less Radix 2 2 Dif Sdf Butterfly For Fast Fourier Transform Structure, Yazan Samir, Rozita Teymourzadeh, Masuri Othman, Shabiul Islam
Fpga Implementation Of Pipeline Digit-Slicing Multiplier-Less Radix 2 2 Dif Sdf Butterfly For Fast Fourier Transform Structure, Yazan Samir, Rozita Teymourzadeh, Masuri Othman, Shabiul Islam
Dr. Rozita Teymourzadeh, CEng.
The need for wireless communication has driven the communication systems to high performance. However, the main bottleneck that affects the communication capability is the Fast Fourier Transform (FFT), which is the core of most modulators. This paper presents FPGA implementation of pipeline digit-slicing multiplier-less radix 22 DIF (Decimation In Frequency) SDF (single path delay feedback) butterfly for FFT structure. The approach taken; in order to reduce computation complexity in butterfly multiplier, digit-slicing multiplier-less technique was utilized in the critical path of pipeline Radix-22 DIF SDF FFT structure. The proposed design focused on the trade-off between the speed and active silicon …
Optimised Toolbox For The Design Of Rotary Reluctance Motors, Grace I, Rozita Teymourzadeh, Bright S, Aravind Cv
Optimised Toolbox For The Design Of Rotary Reluctance Motors, Grace I, Rozita Teymourzadeh, Bright S, Aravind Cv
Dr. Rozita Teymourzadeh, CEng.
Operation of the rotary reluctance machine is highly affected due to the sequential attraction-repulsion principle of the adjacent phase excitation. The problem has been identified and addressed by various researchers in the past decades. Effective magnetic design is one way of minimizing the effect. However it is tedious and time consuming as the design procedure involve higher analytical derivation and calculations. This paper presents a simpler graphical user interface toolbox to use for the design of reluctance motors. The developed interface calculates the analytical values of the aligned, unaligned and intermediate inductance values so that the user can interpret the …
The Effect Of The Digit Slicing Architecture On The Fft Butterfly, Yazan Samir, Rozita Teymourzadeh
The Effect Of The Digit Slicing Architecture On The Fft Butterfly, Yazan Samir, Rozita Teymourzadeh
Dr. Rozita Teymourzadeh, CEng.
Most communications systems tend to achieve bandwidth, power and cost efficiencies to capable to describe modulation scheme. Hence for signal modulation orthogonal frequency division multiplexing (OFDM) transceiver is introduced to cover communications demand in four generation. However high performance Fast Fourier Transforms (FFT) as a main heart of OFDM acts beyond the view. In order to achieve capable FFT, design and realization of its efficient internal structure is key issues of this research work. In this paper implementation of high performance butterfly for FFT by applying digit slicing technique is presented. The proposed design focused on the trade-off between the …
Vlsi Implementation Of Novel Class Of High Speed Pipelined Digital Signal Processing Filter For Wireless Receivers, Rozita Teymourzadeh, Yazan Samir, Shabuil Islam, Masuri Othman, Mok Vh
Vlsi Implementation Of Novel Class Of High Speed Pipelined Digital Signal Processing Filter For Wireless Receivers, Rozita Teymourzadeh, Yazan Samir, Shabuil Islam, Masuri Othman, Mok Vh
Dr. Rozita Teymourzadeh, CEng.
The need for high performance transceiver with high Signal to Noise Ratio (SNR) has driven the communication system to utilize latest technique identified as over sampling systems. It was the most economical modulator and decimation in communication system. It has been proven to increase the SNR and is used in many high performance systems such as in the Analog to Digital Converter (ADC) for wireless transceiver. This research work presented the design of the novel class of decimation and its VLSI implementation which was the sub-component in the over sampling technique. The design and realization of main unit of decimation …
Design Of Automatic Soil Humidity Control Using Maximum Power Point Tracking Controller, Hoe Ck, Vaithlingam A.C., Rozita Teymourzadeh, Rajkumar R
Design Of Automatic Soil Humidity Control Using Maximum Power Point Tracking Controller, Hoe Ck, Vaithlingam A.C., Rozita Teymourzadeh, Rajkumar R
Dr. Rozita Teymourzadeh, CEng.
The photovoltaic system uses the photovoltaic array as a source of electrical power for the direct conversion of the sun’s radiation to direct current without any environmental hazards. The main purpose of this research is to design of a converter with Maximum Power Point Tracker (MPPT) algorithm for any typical application of soil humidity control. Using this setup the major energy from the solar panel is used for the control of soil humidity. The design of the converter with MPPT together with the soil humidity control logic is presented in this paper. Experimental testing of the design controller is implemented …
On-Chip Implementation Of Pipeline Digit-Slicing Multiplier-Less Butterfly For Fast Fourier Transform Architecture, Yazan Samir, Rozita Teymourzadeh, Masuri Othman, Shabiul Islam, Mok Vh
On-Chip Implementation Of Pipeline Digit-Slicing Multiplier-Less Butterfly For Fast Fourier Transform Architecture, Yazan Samir, Rozita Teymourzadeh, Masuri Othman, Shabiul Islam, Mok Vh
Dr. Rozita Teymourzadeh, CEng.
The need for wireless communication has driven the communication systems to high performance. However, the main bottleneck that affects the communication capability is the Fast Fourier Transform (FFT), which is the core of most modulators. This study presents on-chip implementation of pipeline digit-slicing multiplier-less butterfly for FFT structure. The approach taken; in order to reduce computation complexity in butterfly, digit-slicing multiplier-less single constant technique was utilized in the critical path of Radix-2 Decimation In Time (DIT) FFT structure. The proposed design focused on the trade-off between the speed and active silicon area for the chip implementation. The new architecture was …
On-Chip Implementation Of High Resolution High Speed Floating Point Adder/Subtractor With Reducing Mean Latency For Ofdm, Rozita Teymourzadeh, Yazan Samir, Nooshin Mahdavi, Masuri Othman
On-Chip Implementation Of High Resolution High Speed Floating Point Adder/Subtractor With Reducing Mean Latency For Ofdm, Rozita Teymourzadeh, Yazan Samir, Nooshin Mahdavi, Masuri Othman
Dr. Rozita Teymourzadeh, CEng.
Fast Fourier transform (FFT) is widely applied in OFDM trance-receiver communications system. Hence Efficient FFT algorithm is always considered. This paper proposed FPGA realization of high resolution high speed low latency floating point adder/subtractor for FFT in OFDM trance-receiver. The design was implemented for 32 bit pipelined adder/subtractor which satisfied IEEE-754 Standard for floating-point Arithmetic. The design was focused on the trade-off between the latency and speed improvement as well as resolution and silicon area for the chip implementation. In order to reduce the critical path and decrease the latency, the novel structure was designed and investigated. Consequently, synthesis report …
Vlsi Implementation Of High Resolution High Speed Low Latency Pipeline Floating Point Adder/Subtractor For Fft Applications, Rozita Teymourzadeh, Burhan Yeop Majlis, Mok Vh, Masuri Othman
Vlsi Implementation Of High Resolution High Speed Low Latency Pipeline Floating Point Adder/Subtractor For Fft Applications, Rozita Teymourzadeh, Burhan Yeop Majlis, Mok Vh, Masuri Othman
Dr. Rozita Teymourzadeh, CEng.
This paper presents on-chip implementation of high speed low latency floating point adder /subtractor with high accuracy performance for FFT in OFDM transceiver. However due to high performance and high resolution, the floating point adder is matched with power network applications as well. The design was implemented for 32-bit pipelined adder/subtractor which satisfied IEEE-754 Standard for floating -point Arithmetic. The design is focused on the trade-off between the latency and speed improvement as well as resolution and silicon area for the chip implementation. In order to reduce the critical path and decrease the latency, the novel structure was designed and …
On-Chip Implementation Of High Speed And High Resolution Pipeline Radix 2 Fft Algorithm, Rozita Teymourzadeh, Masuri Othman
On-Chip Implementation Of High Speed And High Resolution Pipeline Radix 2 Fft Algorithm, Rozita Teymourzadeh, Masuri Othman
Dr. Rozita Teymourzadeh, CEng.
A new on-chip implementation of Fast Fourier Transform (FFT) based on Radix 2 is presented. The pipeline and parallel approaches are combined to introduce a new high speed FFT algorithm which increases resolution by using floating point calculations in its structures. The design has the merits of low complexity and high speed performance. Furthermore, latency reduction is an important issue to implement the high speed FFT on FPGA. The proposed FFT algorithm shows the latency of (N/2 log(2) N) + 11. Moreover, this algorithm has the advantage of low mean squared error (MSE) of 0.0001 which is preferable to Radix …
Vlsi Implementation Of High Speed And High Resolution Fft Algorithm Based On Radix 2 For Dsp Application, Nooshin Mahdavi, Rozita Teymourzadeh, Masuri Othman
Vlsi Implementation Of High Speed And High Resolution Fft Algorithm Based On Radix 2 For Dsp Application, Nooshin Mahdavi, Rozita Teymourzadeh, Masuri Othman
Dr. Rozita Teymourzadeh, CEng.
Using Fast Fourier Transform (FFT) is indispensable in most signal processing applications. Designing an appropriate algorithm for the implementation of FFT can be efficacious in digital signal processing. Sophisticated techniques such as pipelining and parallel calculations have potential impacts on VLSI implementation of FFT algorithm. Furthermore, a mathematic approach such as floating point calculation achieves higher precision. In this paper, an efficient algorithm with using parallel and pipelining methods is proposed to implement high speed and high resolution FFT algorithm. Latency reduction is an important issue to implement the high speed FFT on FPGA. The Proposed FFT algorithm shows the …
An Enhancement Of Decimation Process Using Fast Cascaded Integrator Comb (Cic), Rozita Teymourzadeh, Masuri Othman
An Enhancement Of Decimation Process Using Fast Cascaded Integrator Comb (Cic), Rozita Teymourzadeh, Masuri Othman
Dr. Rozita Teymourzadeh, CEng.
The over sampling technique has been shown to increase the SNR and is used in many high performance system such as in the ADC for audio and DAT systems. This paper presents the design of the decimation and its VLSI implementation which is the sub-component in the over sampling technique. The design of three main units in the decimation stage that is the Cascaded Integrator Comb (CIC) filter, the associated half band filters and the droop correction are also described. The Verilog HDL code in Xilinx ISE environment has been derived to describe the CIC filter properties and downloaded in …
An Overview Of The Decimation Process And Its Vlsi Implementation, Rozita Teymourzadeh, Masuri Othman
An Overview Of The Decimation Process And Its Vlsi Implementation, Rozita Teymourzadeh, Masuri Othman
Dr. Rozita Teymourzadeh, CEng.
Digital Decimation process plays an important task in communication system. It mostly is applied in transceiver when the frequency reduction is required. However, the decimation process for sigma delta modulator is considered in this research work. The proposed design was simulated using MATLAB software and implemented by hardware description language in Xilinx environment. Furthermore, the proposed advance arithmetic unit is applied to improve the system efficiency.
An Improved Recursive And Non-Recursive Comb Filter For Dsp Applications, Rozita Teymourzadeh, Masuri Othman
An Improved Recursive And Non-Recursive Comb Filter For Dsp Applications, Rozita Teymourzadeh, Masuri Othman
Dr. Rozita Teymourzadeh, CEng.
The recursive and non-recursive comb filters are commonly used as decimators for the sigma delta modulators. This paper presents the analysis and design of low power and high speed comb filters. The comparison is made between the recursive and the non-recursive comb filters with the focus on high speed and saving power consumption. Design procedures and examples are given by using Matlab and Verilog HDL for both recursive and non-recursive comb filter with emphasis on frequency response, transfer function and register width. The implementation results show that non-recursive comb filter has capability of speeding up the circuit and reducing power …
Vlsi Implementation Of Cascaded Integrator Comb Filters For Dsp Applications, Rozita Teymourzadeh, Masuri Othman
Vlsi Implementation Of Cascaded Integrator Comb Filters For Dsp Applications, Rozita Teymourzadeh, Masuri Othman
Dr. Rozita Teymourzadeh, CEng.
The recursive comb filters or Cascaded Integrator Comb filter (CIC) are commonly used as decimators for the sigma delta modulators. This paper presents the VLSI implementation, analysis and design of high speed CIC filters which are based on a low-pass filter. These filters are used in the signal decimation which has the effect on reducing the sampling rate. It is also chosen because its attractive property of both low power and low complexity since it dose not required a multiplier. Simulink toolbox available in Matlab software which is used to simulator and Verilog HDL coding help to verify the functionality …
On-Chip Implementation Of Cascaded Integrated Comb Filters (Cic) For Dsp Application, Rozita Teymourzadeh, Masuri Othman
On-Chip Implementation Of Cascaded Integrated Comb Filters (Cic) For Dsp Application, Rozita Teymourzadeh, Masuri Othman
Dr. Rozita Teymourzadeh, CEng.
This paper presents the design of a CIC filters based on a low-pass filter for reducing the sampling rate, also known as decimation process. The targeted application for the filter is in the analog to digital conversion (ADC).The CIC is chosen because of its attractive property of both low power and complexity since it dose not required multipliers. Simulink toolbox available in Matlab software is used to design and simulate the functionality of the CIC filter. This paper also shows how sample frequency is decreased by CIC filter and it can be used to give enough stop-band attenuation to prevent …