Computer Engineering Commons^™

Virtual Prototyping Of Pebb Based Power Electronics System For Ground Vehicles, Yi Li

All Theses

Power electronics are heavily involved in power and energy systems in plenty of applications nowadays. The increase of demand brings more challenges into simulations for development. Considering the complexity of the systems and high frequency operational conditions, this paper presents comprehensive research on modeling, simulating, and validation on ground vehicle propulsion system applications.

To reduce the computational burden, the Power Electronics Building Blocks concept is utilized to simplify the structure of modeling under different conversion scenarios in ground vehicle systems. In addition, the Average and Switching versions models are included. To speedup the simulation, the engagement of advanced computing technique …

Therapeutic Mechanical Horse, Cade M. Liberty, Aleya Dolorfino, Peter Philips, Zuzanna Dominik, Luke Watts

Mechanical Engineering

Jack's Helping Hand and its hippotherapy participants required a device to serve as an alternative to a live horseback riding experience that could also increase the range of riders. This would provide more clients with equine-assisted therapy that has proven to better the lives of people with both physical and mental disabilities. Horses can be unpredictable, tall, and sometimes anxiety-inducing, especially for new riders. Our group’s aim was to develop a mechanical horse that will be able to reduce these issues for equine therapy centers and the riders they help. When a rider gets to practice sitting on the horse …

Parallel Multi-Core Verilog Hdl Simulation, Tariq B. Ahmad

Doctoral Dissertations

In the era of multi-core computing, the push for creating true parallel applications that can run on individual CPUs is on the rise. Application of parallel discrete event simulation (PDES) to hardware design verification looks promising, given the complexity of today’s hardware designs. Unfortunately, the challenges imposed by lack of inherent parallelism, suboptimal design partitioning, synchronization and communication overhead, and load balancing, render this approach largely ineffective. This thesis presents three techniques for accelerating simulation at three levels of abstraction namely, RTL, functional gate-level (zero-delay) and gate-level timing. We review contemporary solutions and then propose new ways of speeding up …

Design Of Cpu Simulation Software For Armv7 Instruction Set Architecture, Dillon Tellier

Computer Engineering

Simulations have long been a part of the engineering process in both the professional and academic domain. From a pedagogic standpoint, simulations allow students to explore the dynamics of engineering scenarios by controlling variables, taking measurements, and observing behavior which would be difficult or impossible without simulation. One such tool is a CPU simulator used in Cal Poly’s Computer Architecture classes; this software simulates an instruction accurate operation of a computer processor and reports statistics regarding the execution of the supplied compiled machine code. For the last several years Cal Poly’s computer architecture classes have used a previous version of …

An Fpga Based Implementation Of The Exact Stochastic Simulation Algorithm, Phani Bharadwaj Vanguri

Masters Theses

Mathematical and statistical modeling of biological systems is a desired goal for many years. Many biochemical models are often evaluated using a deterministic approach, which uses differential equations to describe the chemical interactions. However, such an approach is inaccurate for small species populations as it neglects the discrete representation of population values, presents the possibility of negative populations, and does not represent the stochastic nature of biochemical systems. The Stochastic Simulation Algorithm (SSA) developed by Gillespie is able to properly account for these inherent noise fluctuations. Due to the stochastic nature of the Monte Carlo simulations, large numbers of simulations …

A Hardware Framework For Yield And Reliability Enhancement In Chip Multiprocessors, Abhisek Pan

Masters Theses 1911 - February 2014

Device reliability and manufacturability have emerged as dominant concerns in end-of-road CMOS devices. Today an increasing number of hardware failures are attributed to device reliability problems that cause partial system failure or shutdown. Also maintaining an acceptable manufacturing yield is seen as challenge because of smaller feature sizes, process variation, and reduced headroom for burn-in tests. In this project we investigate a hardware-based scheme for improving yield and reliability of a homogeneous chip multiprocessor (CMP). The proposed solution involves a hardware framework that enables us to utilize the redundancies inherent in a multi-core system to keep the system operational in …

Robust Control Techniques Enabling Duty Cycle Experiments Utilizing A 6-Dof Crewstation Motion Base, A Full Scale Combat Hybrid Electric Power System, And Long Distance Internet Communications, Marc Compere, Jarrett Goodell, Miguel Simon, Wilford Smith, Mark Brudnak

Publications

The RemoteLink effort supports the U.S. Army's objective for developing and fielding next generation hybrid-electric combat vehicles. It is a distributed soldierin- the-Ioop and hardware-in-the-Ioop environment with a 6-DOF motion base for operator realism, a full-scale combat hybrid electric power system, and an operational context provided by OneSAF. The driver/gunner crewstations rest on one of two 6-DOF motion bases at the U.S. Army TARDEC Simulation Laboratory (TSL). The hybrid power system is located 2,450 miles away at the TARDEC Power and Energy System Integration Laboratory (P&E SIL). The primary technical challenge in the RemoteLink is to operate both laboratories together …

Robust Control Techniques For State Tracking In The Presence Of Variable Time Delays, Jarrett Goodell, Marc Compere, Miguel Simon, Wilford Smith, Ronnie Wright, Mark Brudnak

Publications

In this paper, a distributed driver-in-the-Ioop and hardware-in-the-Ioop simulator is described with a driver on a motion simulator at the U.S. Army TARDEC Ground Vehicle Simulation Laboratory (GVSL). Realistic power system response is achieved by linking the driver in the GVSL with a full-sized hybrid electric power system located 2,450 miles away at the TARDEC Power and Energy Systems Integration Laboratory (P&E SIL), which is developed and maintained by Science Applications International Corporation (SAIC). The goal is to close the loop between the GVSL and P&E SIL over the Internet to provide a realistic driving experience in addition to realistic …