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Articles 31 - 60 of 82
Full-Text Articles in Computer Engineering
A Proposed Approach To Hybrid Software-Hardware Application Design For Enhanced Application Performance, Alex Shipman
A Proposed Approach To Hybrid Software-Hardware Application Design For Enhanced Application Performance, Alex Shipman
Graduate Theses and Dissertations
One important aspect of many commercial computer systems is their performance; therefore, system designers seek to improve the performance next-generation systems with respect to previous generations. This could mean improved computational performance, reduced power consumption leading to better battery life in mobile devices, smaller form factors, or improvements in many areas. In terms of increased system speed and computation performance, processor manufacturers have been able to increase the clock frequency of processors up to a point, but now it is more common to seek performance gains through increased parallelism (such as a processor having more processor cores on a single …
Scalable High-Speed Communications For Neuromorphic Systems, Aaron Reed Young
Scalable High-Speed Communications For Neuromorphic Systems, Aaron Reed Young
Masters Theses
Field-programmable gate arrays (FPGA), application-specific integrated circuits (ASIC), and other chip/multi-chip level implementations can be used to implement Dynamic Adaptive Neural Network Arrays (DANNA). In some applications, DANNA interfaces with a traditional computing system to provide neural network configuration information, provide network input, process network outputs, and monitor the state of the network. The present host-to-DANNA network communication setup uses a Cypress USB 3.0 peripheral controller (FX3) to enable host-to-array communication over USB 3.0. This communications setup has to run commands in batches and does not have enough bandwidth to meet the maximum throughput requirements of the DANNA device, resulting …
Tiled Danna: Dynamic Adaptive Neural Network Array Scaled Across Multiple Chips, Patricia Jean Eckhart
Tiled Danna: Dynamic Adaptive Neural Network Array Scaled Across Multiple Chips, Patricia Jean Eckhart
Masters Theses
Tiled Dynamic Adaptive Neural Network Array(Tiled DANNA) is a recurrent spiking neural network structure composed of programmable biologically inspired neurons and synapses that scales across multiple FPGA chips. Fire events that occur on and within DANNA initiate spiking behaviors in the programmable elements allowing DANNA to hold memory through the synaptic charge propagation and neuronal charge accumulation. DANNA is a fully digital neuromorphic computing structure based on the NIDA architecture. To support initial prototyping and testing of the Tiled DANNA, multiple Xilinx Virtex 7 690Ts were leveraged. The primary goal of Tiled DANNA is to support scaling of DANNA neural …
General-Purpose Digital Filter Platform, Michael Cheng
General-Purpose Digital Filter Platform, Michael Cheng
Electrical Engineering
This senior project provides a platform for high-speed, general-purpose digital filter implementation. EE 459 currently implements digital filters using reprogrammable digital signal processor boards. These aging digital signal processors serially calculate each difference equation term. Operating at 1 Mega-sample per second, the new general-purpose platform simultaneously processes at least ten digital filtering difference equation coefficients. The platform also features an audio jack input and BNC connectors for viewing input and output signals. The filter digitizes single channel audio signals at 44.1 kHz sampling rate with 16-bit precision or 1 MHz sampling at 8-bit precision. The new reprogrammable platform includes a …
A Hybrid Partially Reconfigurable Overlay Supporting Just-In-Time Assembly Of Custom Accelerators On Fpgas, Zeyad Tariq Aklah
A Hybrid Partially Reconfigurable Overlay Supporting Just-In-Time Assembly Of Custom Accelerators On Fpgas, Zeyad Tariq Aklah
Graduate Theses and Dissertations
The state of the art in design and development flows for FPGAs are not sufficiently mature to allow programmers to implement their applications through traditional software development flows. The stipulation of synthesis as well as the requirement of background knowledge on the FPGAs' low-level physical hardware structure are major challenges that prevent programmers from using FPGAs. The reconfigurable computing community is seeking solutions to raise the level of design abstraction at which programmers must operate, and move the synthesis process out of the programmers' path through the use of overlays. A recent approach, Just-In-Time Assembly (JITA), was proposed that enables …
Network-On-Chip Based H.264 Video Decoder On A Field Programmable Gate Array, Ian Barge
Network-On-Chip Based H.264 Video Decoder On A Field Programmable Gate Array, Ian Barge
Master's Theses (2009 -)
This thesis develops the first fully network-on-chip (NoC) based h.264 video decoder implemented in real hardware on a field programmable gate array (FPGA). This thesis starts with an overview of the h.264 video coding standard and an introduction to the NoC communication paradigm. Following this, a series of processing elements (PEs) are developed which implement the component algorithms making up the h.264 video decoder. These PEs, described primarily in VHDL with some Verilog and C, are then mapped to an NoC which is generated using the CONNECT NoC generation tool. To demonstrate the scalability of the proposed NoC based design, …
Modeling And Control Of A Permanent-Magnet Brushless Dc Motor Drive Using A Fractional Order Proportional-Integral-Derivative Controller, Swapnil Khubalkar, Anjali Junghare, Mohan Aware, Shantanu Das
Modeling And Control Of A Permanent-Magnet Brushless Dc Motor Drive Using A Fractional Order Proportional-Integral-Derivative Controller, Swapnil Khubalkar, Anjali Junghare, Mohan Aware, Shantanu Das
Turkish Journal of Electrical Engineering and Computer Sciences
This paper deals with the speed control of a permanent-magnet brushless direct current (PMBLDC) motor. A fractional order PID (FOPID) controller is used in place of the conventional PID controller. The FOPID controller is a generalized form of the PID controller in which the order of integration and differentiation is any real number. It is shown that the proposed controller provides a powerful framework to control the PMBLDC motor. Parameters of the controller are found by using a novel dynamic particle swarm optimization (dPSO) method. The frequency domain pole-zero (p-z) interlacing method is used to approximate the fractional order operator. …
Exploiting Hardware Abstraction For Parallel Programming Framework: Platform And Multitasking, Hongyuan Ding
Exploiting Hardware Abstraction For Parallel Programming Framework: Platform And Multitasking, Hongyuan Ding
Graduate Theses and Dissertations
With the help of the parallelism provided by the fine-grained architecture, hardware accelerators on Field Programmable Gate Arrays (FPGAs) can significantly improve the performance of many applications. However, designers are required to have excellent hardware programming skills and unique optimization techniques to explore the potential of FPGA resources fully. Intermediate frameworks above hardware circuits are proposed to improve either performance or productivity by leveraging parallel programming models beyond the multi-core era.
In this work, we propose the PolyPC (Polymorphic Parallel Computing) framework, which targets enhancing productivity without losing performance. It helps designers develop parallelized applications and implement them on FPGAs. …
Analysis Of 3d Cone-Beam Ct Image Reconstruction Performance On A Fpga, Devin Held
Analysis Of 3d Cone-Beam Ct Image Reconstruction Performance On A Fpga, Devin Held
Electronic Thesis and Dissertation Repository
Efficient and accurate tomographic image reconstruction has been an intensive topic of research due to the increasing everyday usage in areas such as radiology, biology, and materials science. Computed tomography (CT) scans are used to analyze internal structures through capture of x-ray images. Cone-beam CT scans project a cone-shaped x-ray to capture 2D image data from a single focal point, rotating around the object. CT scans are prone to multiple artifacts, including motion blur, streaks, and pixel irregularities, therefore must be run through image reconstruction software to reduce visual artifacts. The most common algorithm used is the Feldkamp, Davis, and …
Architecture For Real-Time, Low-Swap Embedded Vision Using Fpgas, Steven Andrew Clukey
Architecture For Real-Time, Low-Swap Embedded Vision Using Fpgas, Steven Andrew Clukey
Masters Theses
In this thesis we designed, prototyped, and constructed a printed circuit board for real-time, low size, weight, and power (SWaP) HDMI video processing and developed a general purpose library of image processing functions for FPGAs.
The printed circuit board is a baseboard for a Xilinx Zynq based system-on-module (SoM). The board provides power, HDMI input, and HDMI output to the SoM and enables low-SWaP, high-resolution, real-time video processing.
The image processing library for FPGAs is designed for high performance and high reusability. These objectives are achieved by utilizing the Chisel hardware construction language to create parameterized modules that construct low-level …
Automatic Arrhythmia Beat Detection: Algorithm, System, And Implementation, Wisnu Jatmiko, I Md. Agus Setiawan, Muhammad Ali Akbar, Muhammad Eka Suryana, Yulistiyan Wardhana, Muhammad Febrian Rachmadi
Automatic Arrhythmia Beat Detection: Algorithm, System, And Implementation, Wisnu Jatmiko, I Md. Agus Setiawan, Muhammad Ali Akbar, Muhammad Eka Suryana, Yulistiyan Wardhana, Muhammad Febrian Rachmadi
Makara Journal of Technology
Cardiac disease is one of the major causes of death in the world. Early diagnose of the symptoms depends on abnormality on heart beat pattern, known as Arrhythmia. A novel fuzzy neuro generalized learning vector quantization for automatic Arrhythmia heart beat classification is proposed. The algorithm is an extension from the GLVQ algorithm that employs a fuzzy logic concept as the discriminant function in order to develop a robust algorithm and improve the classification performance. The algorithm is tested against MIT-BIH arrhythmia database to measure the performance. Based on the experiment result, FN-GLVQ is able to increase the accuracy of …
A Low Cost Timing Generation Unit, Christopher Vochoska
A Low Cost Timing Generation Unit, Christopher Vochoska
Computer Engineering
No abstract provided.
Software Defined Multi-Spectral Imaging For Arctic Sensor Networks, Sam B. Siewert, Matthew Demi Vis, Ryan Claus, Vivek Angoth, Karthikeyan Mani, Kenrick Mock, Surjith B. Singh, Saurav Srivistava, Chris Wagner
Software Defined Multi-Spectral Imaging For Arctic Sensor Networks, Sam B. Siewert, Matthew Demi Vis, Ryan Claus, Vivek Angoth, Karthikeyan Mani, Kenrick Mock, Surjith B. Singh, Saurav Srivistava, Chris Wagner
Publications
Availability of off-the-shelf infrared sensors combined with high definition visible cameras has made possible the construction of a Software Defined Multi-Spectral Imager (SDMSI) combining long-wave, near-infrared and visible imaging. The SDMSI requires a real-time embedded processor to fuse images and to create real-time depth maps for opportunistic uplink in sensor networks. Researchers at Embry Riddle Aeronautical University working with University of Alaska Anchorage at the Arctic Domain Awareness Center and the University of Colorado Boulder have built several versions of a low-cost drop-in-place SDMSI to test alternatives for power efficient image fusion. The SDMSI is intended for use in field …
High Dynamic Performance Of A Bldc Motor With A Front End Converter Using An Fpga Based Controller For Electric Vehicle Application, Praveen Yadav, Rajesh Poola, Khaja Najumudeen
High Dynamic Performance Of A Bldc Motor With A Front End Converter Using An Fpga Based Controller For Electric Vehicle Application, Praveen Yadav, Rajesh Poola, Khaja Najumudeen
Turkish Journal of Electrical Engineering and Computer Sciences
This paper focus on a novel operation of a brushless dc (BLDC) motor fed by a proportional integral (PI) controlled buck--boost converter supplemented with a battery to provide the required power to drive the BLDC motor. The operational characteristics of the proposed BLDC motor drive system for constant as well as step changes in dc link voltage of a front end converter controlled by a Xilinx System Generator (XSG) based PI controller for two quadrant operations are derived. Thus a field programmable gate array (FPGA) based PI controller manages the energy flow through the battery and the front end converter. …
Fpga Implementation Of A Hevc Deblocking Filter For Fast Processing Of Super High Resolution Applications, Awais Khan, Gulistan Raja
Fpga Implementation Of A Hevc Deblocking Filter For Fast Processing Of Super High Resolution Applications, Awais Khan, Gulistan Raja
Turkish Journal of Electrical Engineering and Computer Sciences
This paper proposes the architecture of a deblocking filter (DBF) that removes blocking artifacts in new emerging High Efficiency Video Coding (HEVC). A parallel architecture for both normal and strong filtering modes of HEVC is proposed. Distributed memories and two data paths increase the parallelism and make the architecture more efficient. The proposed architecture is described by Verilog and implemented on FPGA. The architecture can realize real time to compute 4K UHD video at 30 fps by using 46.65 million clocks with total equivalent gate count of 46K. The maximum delay time for output to come after taking input for …
Implementation Of A Modified Svpwm-Based Three-Phase Inverter With Reduced Switches Using A Single Dc Source For A Grid-Connected Pv System, Venkatesan Mani, Rajeswari Ramachandran, Deverajan Nanjundappan
Implementation Of A Modified Svpwm-Based Three-Phase Inverter With Reduced Switches Using A Single Dc Source For A Grid-Connected Pv System, Venkatesan Mani, Rajeswari Ramachandran, Deverajan Nanjundappan
Turkish Journal of Electrical Engineering and Computer Sciences
No abstract provided.
An Alternative Carry-Save Arithmetic For New Generation Field Programmable Gate Arrays, Uğur Çi̇ni̇, Mustafa Aktan, Avni̇ Morgül
An Alternative Carry-Save Arithmetic For New Generation Field Programmable Gate Arrays, Uğur Çi̇ni̇, Mustafa Aktan, Avni̇ Morgül
Turkish Journal of Electrical Engineering and Computer Sciences
In this work, a double carry-save addition operation is proposed, which is efficiently synthesized for 6-input LUT-based field programmable gate arrays (FPGAs). The proposed arithmetic operation is based on redundant number representation and provides carry propagation-free addition. Using the proposed arithmetic operation, a compact and fast multiply and accumulate unit is designed. To our knowledge, the proposed design provides the fastest multiply-add operation for 6-input LUT-based FPGA systems. A finite impulse response filter implementation is given to show the performance of the proposed structure. The proposed implementation provides a dramatic performance increase, which is at least 2 times faster than …
A High Performance Architecture For An Exact Match Short-Read Aligner Using Burrows-Wheeler Aligner On Fpgas, Dana Abdul Qader
A High Performance Architecture For An Exact Match Short-Read Aligner Using Burrows-Wheeler Aligner On Fpgas, Dana Abdul Qader
Masters Theses
Due to modern DNA sequencing technologies vast amount of short DNA sequences known as short-reads is generated. Biologists need to be able to align the short-reads to a reference genome to be able to make scientific use of the data. Fast and accurate short-read aligner programs are needed to keep up with the pace at which this data is generated. Field Programmable Gate Arrays have been widely used to accelerate many data-intensive bioinformatics applications.
Burrows-Wheeler Transform has been used in the theory of string matching which has led to the development of many short-read alignment programs. This thesis presents a …
Signage Recognition Based Wayfinding System For The Visually Impaired, Abdullah Khalid Ahmed
Signage Recognition Based Wayfinding System For The Visually Impaired, Abdullah Khalid Ahmed
Masters Theses
Persons of visual impairment make up a growing segment of modern society. To cater to the special needs of these individuals, society ought to consider the design of special constructs to enable them to fulfill their daily necessities. This research proposes a new method for text extraction from indoor signage that will help persons of visual impairment maneuver in unfamiliar indoor environments, thus enhancing their independence and quality of life.
In this thesis, images are acquired through a video camera mounted on glasses of the walking person. Frames are then extracted and used in an integrated framework that applies Maximally …
Design And Implementation Of A High Performance Network Processor With Dynamic Workload Management, Padmaja Duggisetty
Design And Implementation Of A High Performance Network Processor With Dynamic Workload Management, Padmaja Duggisetty
Masters Theses
Internet plays a crucial part in today's world. Be it personal communication, business transactions or social networking, internet is used everywhere and hence the speed of the communication infrastructure plays an important role. As the number of users increase the network usage increases i.e., the network data rates ramped up from a few Mb/s to Gb/s in less than a decade. Hence the network infrastructure needed a major upgrade to be able to support such high data rates. Technological advancements have enabled the communication links like optical fibres to support these high bandwidths, but the processing speed at the nodes …
An Investigation Into Partitioning Algorithms For Automatic Heterogeneous Compilers, Antonio M. Leija
An Investigation Into Partitioning Algorithms For Automatic Heterogeneous Compilers, Antonio M. Leija
Master's Theses
Automatic Heterogeneous Compilers allows blended hardware-software solutions to be explored without the cost of a full-fledged design team, but limited research exists on current partitioning algorithms responsible for separating hardware and software. The purpose of this thesis is to implement various partitioning algorithms onto the same automatic heterogeneous compiler platform to create an apples to apples comparison for AHC partitioning algorithms. Both estimated outcomes and actual outcomes for the solutions generated are studied and scored. The platform used to implement the algorithms is Cal Poly’s own Twill compiler, created by Doug Gallatin last year. Twill’s original partitioning algorithm is chosen …
Towards Real-Time, On-Board, Hardware-Supported Sensor And Software Health Management For Unmanned Aerial Systems, Johann M. Schumann, Kristin Y. Rozier, Thomas Reinbacher, Ole J. Mengshoel, Timmy Mbaya, Corey Ippolito
Towards Real-Time, On-Board, Hardware-Supported Sensor And Software Health Management For Unmanned Aerial Systems, Johann M. Schumann, Kristin Y. Rozier, Thomas Reinbacher, Ole J. Mengshoel, Timmy Mbaya, Corey Ippolito
Ole J Mengshoel
Designing And Implementing A Reliable Thermal Monitoring System Based On The 1-Wire Protocol On Fpga For A Leo Satellite, Reza Omidi Gosheblagh, Karim Mohammadi
Designing And Implementing A Reliable Thermal Monitoring System Based On The 1-Wire Protocol On Fpga For A Leo Satellite, Reza Omidi Gosheblagh, Karim Mohammadi
Turkish Journal of Electrical Engineering and Computer Sciences
Thermal control and monitoring is one of the most important factors in the design of satellite systems. An appropriate thermal design should make sure that the satellite's sensitive components remain in their nominated range, even under the vacuum condition of outer space. To achieve this purpose, a reliable and stable monitoring system is required. This paper proposes a monitoring system based on the 1-wire protocol, which provides the reliability requirements in the sensor networking and bus controller sections. In the networking section, we outline some practical topologies and discuss on their complexity and reliability. Despite the fact that the point-to-point …
Optimizing Performance And Scalability On Hybrid Mpsocs, Hongyuan Ding
Optimizing Performance And Scalability On Hybrid Mpsocs, Hongyuan Ding
Graduate Theses and Dissertations
Hardware accelerators are capable of achieving significant performance improvement. But design- ing hardware accelerators lacks the flexibility and the productivity. Combining hardware accelerators with multiprocessor system-on-chip (MPSoC) is an alternative way to balance the flexibility, the productivity, and the performance. However, without appropriate programming model it is still a challenge to achieve parallelism on a hybrid (MPSoC) with with both general-purpose processors and dedicated accelerators. Besides, increasing computation demands with limited power budget require more energy-efficient design without performance degradation in embedded systems and mobile computing platforms. Reconfigurable computing with emerging storage technologies is an alternative to enable the optimization …
Hardware Certification For Real-Time Safety-Critical Systems: State Of The Art, Andrew J. Kornecki, Janusz Zalewski
Hardware Certification For Real-Time Safety-Critical Systems: State Of The Art, Andrew J. Kornecki, Janusz Zalewski
Andrew J. Kornecki
This paper discusses issues related to the RTCA document DO-254 Design Assurance Guidance for Airborne Electronic Hardware and its consequences for hardware certification. In particular, problems related to circuits’ compliance with DO-254 in avionics and other industries are considered. Extensive literature review of the subject is given, including current views on and experiences of chip manufacturers and EDA industry with qualification of hardware design tools, including formal approaches to hardware verification. Some results of the authors’ own study on tool qualification are presented.
Twill: A Hybrid Microcontroller-Fpga Framework For Parallelizing Single- Threaded C Programs, Douglas S. Gallatin
Twill: A Hybrid Microcontroller-Fpga Framework For Parallelizing Single- Threaded C Programs, Douglas S. Gallatin
Master's Theses
Increasingly System-On-A-Chip platforms which incorporate both micropro- cessors and re-programmable logic are being utilized across several fields ranging from the automotive industry to network infrastructure. Unfortunately, the de- velopment tools accompanying these products leave much to be desired, requiring knowledge of both traditional embedded systems languages like C and hardware description languages like Verilog. We propose to bridge this gap with Twill, a truly automatic hybrid compiler that can take advantage of the parallelism inherent in these platforms. Twill can extract long-running threads from single threaded C code and distribute these threads across the hardware and software domains to more …
An Open Source, Line Rate Datagram Protocol Facilitating Message Resiliency Over An Imperfect Channel, Christina Marie Smith
An Open Source, Line Rate Datagram Protocol Facilitating Message Resiliency Over An Imperfect Channel, Christina Marie Smith
Graduate Theses and Dissertations
Remote Direct Memory Access (RDMA) is the transfer of data into buffers between two compute nodes that does not require the involvement of a CPU or Operating System (OS). The idea is borrowed from Direct Memory Access (DMA) which allows memory within a compute node to be transferred without transiting through the CPU. RDMA is termed a zero-copy protocol as it eliminates the need to copy data between buffers within the protocol stack. Because of this and other features, RDMA promotes reliable, high throughput and low latency transfer for packet-switched networking. While the benefits of RMDA are well known and …
Reconfigurable Technologies For Next Generation Internet And Cluster Computing, Deepak C. Unnikrishnan
Reconfigurable Technologies For Next Generation Internet And Cluster Computing, Deepak C. Unnikrishnan
Open Access Dissertations
Modern web applications are marked by distinct networking and computing characteristics. As applications evolve, they continue to operate over a large monolithic framework of networking and computing equipment built from general-purpose microprocessors and Application Specific Integrated Circuits (ASICs) that offers few architectural choices. This dissertation presents techniques to diversify the next-generation Internet infrastructure by integrating Field-programmable Gate Arrays (FPGAs), a class of reconfigurable integrated circuits, with general-purpose microprocessor-based techniques. Specifically, our solutions are demonstrated in the context of two applications - network virtualization and distributed cluster computing.
Network virtualization enables the physical network infrastructure to be shared among several …
Applied Hw/Sw Co-Design: Using The Kendall Tau Algorithm For Adaptive Pacing, Kenneth W. Chee
Applied Hw/Sw Co-Design: Using The Kendall Tau Algorithm For Adaptive Pacing, Kenneth W. Chee
Master's Theses
Microcontrollers, the brains of embedded systems, have found their way into every aspect of our lives including medical devices such as pacemakers. Pacemakers provide life supporting functions to people therefore it is critical for these devices to meet their timing constraints. This thesis examines the use of hardware co-processing to accelerate the calculation time associated with the critical tasks of a pacemaker. In particular, we use an FPGA to accelerate a microcontroller’s calculation time of the Kendall Tau Rank Correlation Coefficient algorithm. The Kendall Tau Rank Correlation Coefficient is a statistical measure that determines the pacemaker’s voltage level for heart …
Design Of An Open-Source Sata Core For Virtex-4 Fpgas, Cory Gorman
Design Of An Open-Source Sata Core For Virtex-4 Fpgas, Cory Gorman
Masters Theses 1911 - February 2014
Many hard drives manufactured today use the Serial ATA (SATA) protocol to communicate with the host machine, typically a PC. SATA is a much faster and much more robust protocol than its predecessor, ATA (also referred to as Parallel ATA or IDE). Many hardware designs, including those using Field-Programmable Gate Arrays (FPGAs), have a need for a long-term storage solution, and a hard drive would be ideal. One such design is the high-speed Data Acquisition System (DAS) created for the NASA Surface Water and Ocean Topography mission. This system utilizes a Xilinx Virtex-4 FPGA. Although the DAS includes a SATA …