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Full-Text Articles in Computer Engineering

Evaluation Of Robust Deep Learning Pipelines Targeting Low Swap Edge Deployment, David Carter Cornett Dec 2021

Evaluation Of Robust Deep Learning Pipelines Targeting Low Swap Edge Deployment, David Carter Cornett

Masters Theses

The deep learning technique of convolutional neural networks (CNNs) has greatly advanced the state-of-the-art for computer vision tasks such as image classification and object detection. These solutions rely on large systems leveraging wattage-hungry GPUs to provide the computational power to achieve such performance. However, the size, weight and power (SWaP) requirements of these conventional GPU-based deep learning systems are not suitable when a solution requires deployment to so called "Edge" environments such as autonomous vehicles, unmanned aerial vehicles (UAVs) and smart security cameras.

The objective of this work is to benchmark FPGA-based alternatives to conventional GPU systems that have the …


Internet Infrastructures For Large Scale Emulation With Efficient Hw/Sw Co-Design, Aiden K. Gula Oct 2021

Internet Infrastructures For Large Scale Emulation With Efficient Hw/Sw Co-Design, Aiden K. Gula

Masters Theses

Connected systems are becoming more ingrained in our daily lives with the advent of cloud computing, the Internet of Things (IoT), and artificial intelligence. As technology progresses, we expect the number of networked systems to rise along with their complexity. As these systems become abstruse, it becomes paramount to understand their interactions and nuances. In particular, Mobile Ad hoc Networks (MANET) and swarm communication systems exhibit added complexity due to a multitude of environmental and physical conditions. Testing these types of systems is challenging and incurs high engineering and deployment costs. In this work, we propose a scalable MANET emulation …


Hardware Acceleration In Image Stitching: Gpu Vs Fpga, Joshua David Edgcombe Jul 2021

Hardware Acceleration In Image Stitching: Gpu Vs Fpga, Joshua David Edgcombe

Masters Theses

Image stitching is a process where two or more images with an overlapping field of view are combined. This process is commonly used to increase the field of view or image quality of a system. While this process is not particularly difficult for modern personal computers, hardware acceleration is often required to achieve real-time performance in low-power image stitching solutions. In this thesis, two separate hardware accelerated image stitching solutions are developed and compared. One solution is accelerated using a Xilinx Zynq UltraScale+ ZU3EG FPGA and the other solution is accelerated using an Nvidia RTX 2070 Super GPU. The image …


Compound Effects Of Clock And Voltage Based Power Side-Channel Countermeasures, Jacqueline Lagasse Jul 2020

Compound Effects Of Clock And Voltage Based Power Side-Channel Countermeasures, Jacqueline Lagasse

Masters Theses

The power side-channel attack, which allows an attacker to derive secret information from power traces, continues to be a major vulnerability in many critical systems. Numerous countermeasures have been proposed since its discovery as a serious vulnerability, including both hardware and software implementations. Each countermeasure has its own drawback, with some of the highly effective countermeasures incurring large overhead in area and power. In addition, many countermeasures are quite invasive to the design process, requiring modification of the design and therefore additional validation and testing to ensure its accuracy. Less invasive countermeasures that do not require directly modifying the system …


Scalable High-Speed Communications For Neuromorphic Systems, Aaron Reed Young Aug 2017

Scalable High-Speed Communications For Neuromorphic Systems, Aaron Reed Young

Masters Theses

Field-programmable gate arrays (FPGA), application-specific integrated circuits (ASIC), and other chip/multi-chip level implementations can be used to implement Dynamic Adaptive Neural Network Arrays (DANNA). In some applications, DANNA interfaces with a traditional computing system to provide neural network configuration information, provide network input, process network outputs, and monitor the state of the network. The present host-to-DANNA network communication setup uses a Cypress USB 3.0 peripheral controller (FX3) to enable host-to-array communication over USB 3.0. This communications setup has to run commands in batches and does not have enough bandwidth to meet the maximum throughput requirements of the DANNA device, resulting …


Tiled Danna: Dynamic Adaptive Neural Network Array Scaled Across Multiple Chips, Patricia Jean Eckhart Aug 2017

Tiled Danna: Dynamic Adaptive Neural Network Array Scaled Across Multiple Chips, Patricia Jean Eckhart

Masters Theses

Tiled Dynamic Adaptive Neural Network Array(Tiled DANNA) is a recurrent spiking neural network structure composed of programmable biologically inspired neurons and synapses that scales across multiple FPGA chips. Fire events that occur on and within DANNA initiate spiking behaviors in the programmable elements allowing DANNA to hold memory through the synaptic charge propagation and neuronal charge accumulation. DANNA is a fully digital neuromorphic computing structure based on the NIDA architecture. To support initial prototyping and testing of the Tiled DANNA, multiple Xilinx Virtex 7 690Ts were leveraged. The primary goal of Tiled DANNA is to support scaling of DANNA neural …


Architecture For Real-Time, Low-Swap Embedded Vision Using Fpgas, Steven Andrew Clukey Dec 2016

Architecture For Real-Time, Low-Swap Embedded Vision Using Fpgas, Steven Andrew Clukey

Masters Theses

In this thesis we designed, prototyped, and constructed a printed circuit board for real-time, low size, weight, and power (SWaP) HDMI video processing and developed a general purpose library of image processing functions for FPGAs.

The printed circuit board is a baseboard for a Xilinx Zynq based system-on-module (SoM). The board provides power, HDMI input, and HDMI output to the SoM and enables low-SWaP, high-resolution, real-time video processing.

The image processing library for FPGAs is designed for high performance and high reusability. These objectives are achieved by utilizing the Chisel hardware construction language to create parameterized modules that construct low-level …


Signage Recognition Based Wayfinding System For The Visually Impaired, Abdullah Khalid Ahmed Dec 2015

Signage Recognition Based Wayfinding System For The Visually Impaired, Abdullah Khalid Ahmed

Masters Theses

Persons of visual impairment make up a growing segment of modern society. To cater to the special needs of these individuals, society ought to consider the design of special constructs to enable them to fulfill their daily necessities. This research proposes a new method for text extraction from indoor signage that will help persons of visual impairment maneuver in unfamiliar indoor environments, thus enhancing their independence and quality of life.

In this thesis, images are acquired through a video camera mounted on glasses of the walking person. Frames are then extracted and used in an integrated framework that applies Maximally …


A High Performance Architecture For An Exact Match Short-Read Aligner Using Burrows-Wheeler Aligner On Fpgas, Dana Abdul Qader Dec 2015

A High Performance Architecture For An Exact Match Short-Read Aligner Using Burrows-Wheeler Aligner On Fpgas, Dana Abdul Qader

Masters Theses

Due to modern DNA sequencing technologies vast amount of short DNA sequences known as short-reads is generated. Biologists need to be able to align the short-reads to a reference genome to be able to make scientific use of the data. Fast and accurate short-read aligner programs are needed to keep up with the pace at which this data is generated. Field Programmable Gate Arrays have been widely used to accelerate many data-intensive bioinformatics applications.

Burrows-Wheeler Transform has been used in the theory of string matching which has led to the development of many short-read alignment programs. This thesis presents a …


Design And Implementation Of A High Performance Network Processor With Dynamic Workload Management, Padmaja Duggisetty Nov 2015

Design And Implementation Of A High Performance Network Processor With Dynamic Workload Management, Padmaja Duggisetty

Masters Theses

Internet plays a crucial part in today's world. Be it personal communication, business transactions or social networking, internet is used everywhere and hence the speed of the communication infrastructure plays an important role. As the number of users increase the network usage increases i.e., the network data rates ramped up from a few Mb/s to Gb/s in less than a decade. Hence the network infrastructure needed a major upgrade to be able to support such high data rates. Technological advancements have enabled the communication links like optical fibres to support these high bandwidths, but the processing speed at the nodes …


An Fpga Based Implementation Of The Exact Stochastic Simulation Algorithm, Phani Bharadwaj Vanguri Dec 2010

An Fpga Based Implementation Of The Exact Stochastic Simulation Algorithm, Phani Bharadwaj Vanguri

Masters Theses

Mathematical and statistical modeling of biological systems is a desired goal for many years. Many biochemical models are often evaluated using a deterministic approach, which uses differential equations to describe the chemical interactions. However, such an approach is inaccurate for small species populations as it neglects the discrete representation of population values, presents the possibility of negative populations, and does not represent the stochastic nature of biochemical systems. The Stochastic Simulation Algorithm (SSA) developed by Gillespie is able to properly account for these inherent noise fluctuations. Due to the stochastic nature of the Monte Carlo simulations, large numbers of simulations …