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Electronic Theses and Dissertations

Clockless

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Full-Text Articles in Computer Engineering

Synthesis Of Self-Resetting Stage Logic Pipelines, Rashad Oreifej Jan 2006

Synthesis Of Self-Resetting Stage Logic Pipelines, Rashad Oreifej

Electronic Theses and Dissertations

As designers began to pack multi-million transistors onto a single chip, their reliance on a global clocking signal to orchestrate the operations of the chip has started to face almost insurmountable difficulties. As a result, designers started to explore clockless circuits to avoid the global clocking problem. Recently, self-resetting circuits implemented in dynamic logic families have been proposed as viable clockless alternatives. While these circuits can produce excellent performances, they display serious limitations in terms of area cost and power consumption. A middle-of-the-road alternative, which can provide a good performance and avoid the limitations seen in dynamic self-resetting circuits, would ...


Design And Synthesis Of Clockless Pipelines Based On Self-Resetting Stage Logic, Abdelhalim Alsharqawi Jan 2005

Design And Synthesis Of Clockless Pipelines Based On Self-Resetting Stage Logic, Abdelhalim Alsharqawi

Electronic Theses and Dissertations

For decades, digital design has been primarily dominated by clocked circuits. With larger scales of integration made possible by improved semiconductor manufacturing techniques, relying on a clock signal to orchestrate logic operations across an entire chip became increasingly difficult. Motivated by this problem, designers are currently considering circuits which can operate without a clock. However, the wide acceptance of these circuits by the digital design community requires two ingredients: (i) a unified design methodology supported by widely available CAD tools, and (ii) a granularity of design techniques suitable for synthesizing large designs. Currently, there is no unified established design methodology ...