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Full-Text Articles in Computer Engineering

Self-Stabilizing Group Membership Protocol, Mahesh Subedi Dec 2010

Self-Stabilizing Group Membership Protocol, Mahesh Subedi

UNLV Theses, Dissertations, Professional Papers, and Capstones

In this thesis, we consider the problem of partitioning a network into groups of bounded diameter.

Given a network of processes X and a constant D, the group partition problem is the problem of finding a D-partition of X, that is, a partition of X into disjoint connected subgraphs, which we call groups, each of diameter no greater than D. The minimal group partition problem is to find a D-partition {G1, ... Gm} of X such that no two groups can be combined; that is, for any Gi and Gj, where i ≠ j, either Gi U Gj is disconnected …


Data Routing In Multicore Processors Using Dimension Increment Method, Arpita H. Kadakia Dec 2010

Data Routing In Multicore Processors Using Dimension Increment Method, Arpita H. Kadakia

UNLV Theses, Dissertations, Professional Papers, and Capstones

A Deadlock-free routing algorithm can be generated for arbitrary interconnection network using the concept of virtual channels but the virtual channels will lead to more complex algorithms and more demands of NOC resource.


In this thesis, we study a Torus topology for NOC application, design its structure and propose a routing algorithm exploiting the characteristics of NOC. We have chosen a typical 16 (4 by 4) routers Torus and propose the corresponding route algorithm. In our algorithm, all the channels are assigned 4 different dimensions (n0,n1,n2 & n3). By following the dimension increment method, we break the dependent route circles, …


A Graph-Based Approach To Symbolic Functional Decomposition Of Finite State Machines, Piotr Szotkowski, Mariusz Rawski, Henry Selvaraj Jun 2009

A Graph-Based Approach To Symbolic Functional Decomposition Of Finite State Machines, Piotr Szotkowski, Mariusz Rawski, Henry Selvaraj

Electrical & Computer Engineering Faculty Research

This paper discusses the symbolic functional decomposition method for implementing finite state machines in field-programmable gate array devices. This method is a viable alternative to the presently widespread two-step approaches to the problem, which consist of separate encoding and mapping stages; the proposed method does not have a separate decomposition step instead, the state's final encoding is introduced gradually on every decomposition iteration. Along with general description of the functional symbolic decomposition method's steps, the paper discusses various algorithms implementing the method and presents an example realisation of the most interesting algorithm. In the end, the paper compares the results …


Text Categorization Based On Apriori Algorithm's Frequent Itemsets, Prathima Madadi May 2009

Text Categorization Based On Apriori Algorithm's Frequent Itemsets, Prathima Madadi

UNLV Theses, Dissertations, Professional Papers, and Capstones

Automatic Text categorization is the task of assigning an electronic document to one or more categories, based on its contents. There are many known techniques to efficiently solve categorization problems. Typically these techniques fall into two distinct methodologies which are either logic based or probabilistic. In recent years, many researchers have tried approaches which area hybrid of these two methodologies.

In this thesis, we deal with document categorization using Apriori Algorithm. The Apriori algorithm was initially developed for data mining and basket analysis applications in the relational databases. Although the technique is logic based, it also relies on the statistical …


Scheduling Architectures For Diffserv Networks With Input Queuing Switches, Mei Yang, Henry Selvaraj, Enyue Lu, Jianping Wang, S. Q. Zheng, Yingtao Jiang Jan 2009

Scheduling Architectures For Diffserv Networks With Input Queuing Switches, Mei Yang, Henry Selvaraj, Enyue Lu, Jianping Wang, S. Q. Zheng, Yingtao Jiang

Electrical & Computer Engineering Faculty Research

ue to its simplicity and scalability, the differentiated services (DiffServ) model is expected to be widely deployed across wired and wireless networks. Though supporting DiffServ scheduling algorithms for output-queuing (OQ) switches have been widely studied, there are few DiffServ scheduling algorithms for input-queuing (IQ) switches in the literaure. In this paper, we propose two algorithms for scheduling DiffServ DiffServ networks with IQ switches: the dynamic DiffServ scheduling (DDS) algorithm and the hierarchical DiffServ scheduling (HDS) algorithm. The basic idea of DDS and HDS is to schedule EF and AF traffic According to Their minimum service rates with the reserved bandwidth …


Free Regions Of Sensor Nodes, Laxmi P. Gewali, Navin Rongatana, Henry Selvaraj, Jan B. Pedersen Jan 2009

Free Regions Of Sensor Nodes, Laxmi P. Gewali, Navin Rongatana, Henry Selvaraj, Jan B. Pedersen

Electrical & Computer Engineering Faculty Research

We introduce the notion of free region of a node in a sensor network. Intuitively, a free region of a node is the connected set of points R in its neighborhood such that the connectivity of the network remains the same when the node is moved to any point in R. We characterize several properties of free regions and develop an efficient algorithm for computing them. We capture free region in terms of related notions called in-free region and out-free region. We present an O(n2) algorithm for constructing the free region of a node, where n is the number of …


Significance Of Logic Synthesis In Fpga-Based Design Of Image And Signal Processing Systems, Mariusz Rawski, Henry Selvaraj, Bogdan J. Falkowski, Tadeusz Luba Jun 2008

Significance Of Logic Synthesis In Fpga-Based Design Of Image And Signal Processing Systems, Mariusz Rawski, Henry Selvaraj, Bogdan J. Falkowski, Tadeusz Luba

Electrical & Computer Engineering Faculty Research

This chapter, taking FIR filters as an example, presents the discussion on efficiency of different implementation methodologies of DSP algorithms targeting modern FPGA architectures. Nowadays, programmable technology provides the possibility to implement digital systems with the use of specialized embedded DSP blocks. However, this technology gives the designer the possibility to increase efficiency of designed systems by exploitation of parallelisms of implemented algorithms. Moreover, it is possible to apply special techniques, such as distributed arithmetic (DA). Since in this approach, general-purpose multipliers are replaced by combinational LUT blocks, it is possible to construct digital filters of very high performance. Additionally, …


Least Squares Support Vector Machine Based Classification Of Abnormalities In Brain Mr Images, S. Thamarai Selvi, D. Selvathi, R. Ramkumar, Henry Selvaraj Mar 2006

Least Squares Support Vector Machine Based Classification Of Abnormalities In Brain Mr Images, S. Thamarai Selvi, D. Selvathi, R. Ramkumar, Henry Selvaraj

Electrical & Computer Engineering Faculty Research

The manual interpretation of MRI slices based on visual examination by radiologist/physician may lead to missing diagnosis when a large number of MRIs are analyzed. To avoid the human error, an automated intelligent classification system is proposed. This research paper proposes an intelligent classification technique to the problem of classifying four types of brain abnormalities viz. Metastases, Meningiomas, Gliomas, and Astrocytomas. The abnormalities are classified based on Two/Three/ Four class classification using statistical and textural features. In this work, classification techniques based on Least Squares Support Vector Machine (LS-SVM) using textural features computed from the MR images of patient are …


Efficient Scheduling For Sdmg Cioq Switches, Mei Yang, S. Q. Zheng Jan 2006

Efficient Scheduling For Sdmg Cioq Switches, Mei Yang, S. Q. Zheng

Electrical & Computer Engineering Faculty Research

Combined input and output queuing (CIOQ) switches are being considered as high-performance switch architectures due to their ability to achieve 100% throughput and perfectly emulate output queuing (OQ) switch performance with a small speedup factor S. To realize a speedup factor S, a conventional CIOQ switch requires the switching fabric and memories to operate S times faster than the line rate. In this paper, we propose to use a CIOQ switch with space-division multiplexing expansion and grouped input/output ports (SDMG CIOQ switch for short) to realize speedup while only requiring the switching fabric and memories to operate at the line …


A Fast And Simple Algorithm For Computing M-Shortest Paths In State Graph, M. Sherwood, Laxmi P. Gewali, Henry Selvaraj, Venkatesan Muthukumar Jan 2004

A Fast And Simple Algorithm For Computing M-Shortest Paths In State Graph, M. Sherwood, Laxmi P. Gewali, Henry Selvaraj, Venkatesan Muthukumar

Electrical & Computer Engineering Faculty Research

We consider the problem of computing m shortest paths between a source node s and a target node t in a stage graph. Polynomial time algorithms known to solve this problem use complicated data structures. This paper proposes a very simple algorithm for computing all m shortest paths in a stage graph efficiently. The proposed algorithm does not use any complicated data structure and can be implemented in a straightforward way by using only array data structure. This problem appears as a sub-problem for planning risk reduced multiple k-legged trajectories for aerial vehicles.


Implementation Of Large Neural Networks Using Decomposition, Henry Selvaraj, H. Niewiadomski, P. Buciak, M. Pleban, Piotr Sapiecha, Tadeusz Luba, Venkatesan Muthukumar Jun 2002

Implementation Of Large Neural Networks Using Decomposition, Henry Selvaraj, H. Niewiadomski, P. Buciak, M. Pleban, Piotr Sapiecha, Tadeusz Luba, Venkatesan Muthukumar

Electrical & Computer Engineering Faculty Research

The article presents methods of dealing with huge data in the domain of neural networks. The decomposition of neural networks is introduced and its efficiency is proved by the authors’ experiments. The examinations of the effectiveness of argument reduction in the above filed, are presented. Authors indicate, that decomposition is capable of reducing the size and the complexity of the learned data, and thus it makes the learning process faster or, while dealing with large data, possible. According to the authors experiments, in some cases, argument reduction, makes the learning process harder.


A General Approach To Boolean Function Decomposition And Its Application In Fpgabased Synthesis, Tadeusz Luba, Henry Selvaraj Jan 1995

A General Approach To Boolean Function Decomposition And Its Application In Fpgabased Synthesis, Tadeusz Luba, Henry Selvaraj

Electrical & Computer Engineering Faculty Research

An effective logic synthesis procedure based on parallel and serial decomposition of a Boolean function is presented in this paper. The decomposition, carried out as the very first step of the .synthesis process, is based on an original representation of the function by a set of r-partitions over the set of minterms. Two different decomposition strategies, namely serial and parallel, are exploited by striking a balance between the two ideas. The presented procedure can be applied to completely or incompletely specified, single- or multiple-output functions and is suitable for different types of FPGAs including XILINX, ACTEL and ALGOTRONIX devices. The …