Computer Engineering Commons^™

The Construction And Characterization Of A Magneto-Optical Trap For Rubidium-87 And Electromagnetically-Induced Transparency In Rubidium-87 In A Vapor Cell, Yu Liu

Honors College Theses

Recent years have observed fast developments in neutral atomic vapor based quantum information storage technology. The technique utilizes light fields in the optical wavelength region as signal carrier and retriever and neutral atomic systems (e.g. single atoms, ensembles of atoms, atom-like defects in solids) as storage media. Photons are robust carriers of information due to their high velocity (c = 2.998 x 10⁸ m/s) and ease of transportation (they propagate rectilinearly with low loss). Their high mobility, however, makes it a challenging task to spatially localize and therefore store them. Atoms (or atom-like systems), on the other hand, can …

On High-Performance Parallel Fixed-Point Decimal Multiplier Designs, Ming Zhu

UNLV Theses, Dissertations, Professional Papers, and Capstones

High-performance, area-efficient hardware implementation of decimal multiplication is preferred to slow software simulations in a number of key scientific and financial application areas, where errors caused by converting decimal numbers into their approximate binary representations are not acceptable.

Multi-digit parallel decimal multipliers involve two major stages: (i) the partial product generation (PPG) stage, where decimal partial products are determined by selecting the right versions of the pre-computed multiples of the multiplicand, followed by (ii) the partial product accumulation (PPA) stage, where all the partial products are shifted and then added together to obtain the final multiplication product. In this thesis, …

Hardware-Software Co-Design, Acceleration And Prototyping Of Control Algorithms On Reconfigurable Platforms, Desta Kumsa Edosa

UNLV Theses, Dissertations, Professional Papers, and Capstones

Differential equations play a significant role in many disciplines of science and engineering. Solving and implementing Ordinary Differential Equations (ODEs) and partial Differential Equations (PDEs) effectively are very essential as most complex dynamic systems are modeled based on these equations. High Performance Computing (HPC) methodologies are required to compute and implement complex and data intensive applications modeled by differential equations at higher speed. There are, however, some challenges and limitations in implementing dynamic system, modeled by non-linear ordinary differential equations, on digital hardware. Modeling an integrator involves data approximation which results in accuracy error if data values are not considered …

Hardware Implementation Of Processor Allocator For Mesh Connected Chip Multiprocessors, Rana Sangram Reddy Marri

UNLV Theses, Dissertations, Professional Papers, and Capstones

The advancements in the semiconductor process technology and the current demand for highly parallel computing has led to the advent of Chip Multiprocessors (CMPs). CMP is the integration of two or more independent processor cores, which can read and execute program instructions, on to a single integrated circuit die. CMPs are the main computing platforms for research and development in parallel and high performance computing environments. They offer minimum inter-core communication latencies as the processor cores are present on a single chip.

The Operating System (OS) plays a key role in using a CMP effectively. The OS should support a …

A Refreshable And Portable E-Braille System For The Blind And Visually Impaired, Mohammad Saadeh, Mohamed Trabia

College of Engineering: Graduate Celebration Programs

• Braille is a communication system to assist the blind and visually impaired.
• Present an approach to measure fingertip forces while identifying Braille characters.
• Implement a force sensory feedback in the device to measure the force developed on the fingertip.
• Introduce a preliminary design for the device.
• Build a prototype for the device and evaluate its functionality and integrate its components

Determining The Validity Of The Nintendo Wii Balance Board As An Assessment Tool For Balance, Sabrina Mae Deans

UNLV Theses, Dissertations, Professional Papers, and Capstones

Context. Application of the Nintendo Wii-fit balance board and its games have been used in Physical Therapy clinics, showing success in individuals with neurological disorders, and has been recommended as a minimum baseline assessment of a symptoms checklist and standardized cognitive and balance assessments for concussion management by the NCAA. However, it still faces challenges of being considered a reliable and consistent tool for producing normative data in the allied healthcare. Because there is little to no evidence for the Wii-fit balance board as a valid balance assessment tool for clinical and/or research usage, the significance of this study is …

Optical Network-On-Chip Architectures And Designs, Lei Zhang

UNLV Theses, Dissertations, Professional Papers, and Capstones

As indicated in the latest version of ITRS roadmap, optical wiring is a viable interconnection technology for future SoC/SiC/SiP designs that can provide broad band data transfer rates unmatchable by the existing metal/low-k dielectric interconnects. In this dissertation study, a set of different optical interconnection architectures are presented for future on-chip optical micro-networks.

Three Optical Network-on-Chip (ONoC) architectures, i.e., Wavelength Routing Optical Network-on-Chip (WRON), Redundant Wavelength Routed Optical Network (RDWRON) and Recursive Wavelength Routed Optical Network (RCWRON) are proposed. They are fully connected networks designed based on passive switching Microring Resonator (MRR) optical switches. Given enough different routing optical wavelengths, …

Data Routing In Multicore Processors Using Dimension Increment Method, Arpita H. Kadakia

UNLV Theses, Dissertations, Professional Papers, and Capstones

A Deadlock-free routing algorithm can be generated for arbitrary interconnection network using the concept of virtual channels but the virtual channels will lead to more complex algorithms and more demands of NOC resource.

In this thesis, we study a Torus topology for NOC application, design its structure and propose a routing algorithm exploiting the characteristics of NOC. We have chosen a typical 16 (4 by 4) routers Torus and propose the corresponding route algorithm. In our algorithm, all the channels are assigned 4 different dimensions (n0,n1,n2 & n3). By following the dimension increment method, we break the dependent route circles, …

Performance Evaluation Of Network-On-Chip Interconnect Architectures, Xinan Zhou

UNLV Theses, Dissertations, Professional Papers, and Capstones

With a communication design style, Network-on-Chips (NoCs) have been proposed as a new Multi-Processor System-on-Chip paradigm. Simulation and functional validation are essential to assess the correctness and performance of the NoC design. In this thesis, a cycle-accurate NoC simulation system in Verilog HDL is developed to evaluate the performance of various NoC architectures. First, a library of NoC components is developed based on an existing design. Each NoC architecture to be evaluated is constructed from the library according to the topology description which specifies the network topology, network size, and routing algorithm. The network performance of four NoC architectures under …