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- Agricultural applications (1)
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- Automotive-grade CMOS camera (1)
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- Census transform algorithm (1)
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- Conference Proceedings (1)
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- FPGA (1)
- FPGA datapath precision optimization (1)
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- Lachesis (1)
- Least significant bit problem (1)
- Low-cost stereo vision implementation (1)
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- Multithreading (1)
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Articles 1 - 18 of 18
Full-Text Articles in Computer Engineering
Verified Ros-Based Deployment Of Platform-Independent Control Systems, Wenrui Meng, Junkil Park, Oleg Sokolsky, Stephanie Weirich, Insup Lee
Verified Ros-Based Deployment Of Platform-Independent Control Systems, Wenrui Meng, Junkil Park, Oleg Sokolsky, Stephanie Weirich, Insup Lee
Oleg Sokolsky
The paper considers the problem of model-based deployment of platform-independent control code on a specific platform. The approach is based on automatic generation of platform-specific glue code from an architectural model of the system. We present a tool, ROSGen, that generates the glue code based on a declarative specification of platform interfaces. Our implementation targets the popular Robot Operating System (ROS) platform. We demonstrate that the code generation process is amenable to formal verification. The code generator is implemented in Coq and relies on the infrastructure provided by the CompCert and VST tool. We prove that the generated code always …
Verified Ros-Based Deployment Of Platform-Independent Control Systems, Wenrui Meng, Junkil Park, Oleg Sokolsky, Stephanie Weirich, Insup Lee
Verified Ros-Based Deployment Of Platform-Independent Control Systems, Wenrui Meng, Junkil Park, Oleg Sokolsky, Stephanie Weirich, Insup Lee
Oleg Sokolsky
The paper considers the problem of model-based deployment of platform-independent control code on a specific platform. The approach is based on automatic generation of platform-specific glue code from an architectural model of the system. We present a tool, ROSGen, that generates the glue code based on a declarative specification of platform interfaces. Our implementation targets the popular Robot Operating System (ROS) platform. We demonstrate that the code generation process is amenable to formal verification. The code generator is implemented in Coq and relies on the infrastructure provided by the CompCert and VST tool. We prove that the generated code always …
At The Tone, The Time Will Be... Unknown – A Perspective On The Evolution Of Time In Telecommunications, Robert Iannucci
At The Tone, The Time Will Be... Unknown – A Perspective On The Evolution Of Time In Telecommunications, Robert Iannucci
Robert A Iannucci
No abstract provided.
Lachesis: A Job Scheduler For The Cray T3e, Allen B. Downey
Lachesis: A Job Scheduler For The Cray T3e, Allen B. Downey
Allen B. Downey
This paper presents the design and implementation of Lachesis, a job scheduler for the Cray T3E. Lachesis was developed at the San Diego Supercomputer Center (SDSC) in an attempt to correct some problems with the scheduling system Cray provides with the T3E.
Low-Cost Stereo Vision On An Fpga, Chris A. Murphy, Daniel Lindquist, Ann Marie Rynning, Thomas Cecil, Sarah Leavitt, Mark L. Chang
Low-Cost Stereo Vision On An Fpga, Chris A. Murphy, Daniel Lindquist, Ann Marie Rynning, Thomas Cecil, Sarah Leavitt, Mark L. Chang
Mark L. Chang
We present a low-cost stereo vision implementation suitable for use in autonomous vehicle applications and designed with agricultural applications in mind. This implementation utilizes the Census transform algorithm to calculate depth maps from a stereo pair of automotive-grade CMOS cameras. The final prototype utilizes commodity hardware, including a Xilinx Spartan-3 FPGA, to process 320times240 pixel images at greater than 150 frames per second and deliver them via a USB 2.0 interface.
Automated Least-Significant Bit Datapath Optimization For Fpgas, Mark L. Chang, Scott Hauck
Automated Least-Significant Bit Datapath Optimization For Fpgas, Mark L. Chang, Scott Hauck
Mark L. Chang
In this paper, we present a method for FPGA datapath precision optimization subject to user-defined area and error constraints. This work builds upon our previous research which presented a methodology for optimizing the dynamic range- the most significant bit position. In this work, we present an automated optimization technique for the least-significant bit position of circuit datapaths. We present results describing the effectiveness of our methods on typical signal and image processing kernels.
Embedded Systems As Datacenters, Robert Iannucci
Embedded Systems As Datacenters, Robert Iannucci
Robert A Iannucci
No abstract provided.
Mitigation Of Control Channel Jamming Under Node Capture Attacks, Patrick Tague, Mingya Li, Radha Poovendran
Mitigation Of Control Channel Jamming Under Node Capture Attacks, Patrick Tague, Mingya Li, Radha Poovendran
Patrick Tague
Availability of service in many wireless networks depends on the ability for network users to establish and maintain communication channels using control messages from base stations and other users. An adversary with knowledge of the underlying communication protocol can mount an efficient denial of service attack by jamming the communication channels used to exchange control messages. The use of spread spectrum techniques can deter an external adversary from such control channel jamming attacks. However, malicious colluding insiders or an adversary who captures or compromises system users are not deterred by spread spectrum, as they know the required spreading sequences. For …
Platform Thinking In Embedded Systems, Robert Iannucci
Platform Thinking In Embedded Systems, Robert Iannucci
Robert A Iannucci
No abstract provided.
Configuring Client Software Using Remote Notification Us:6219698, Robert Iannucci, Chris Weikart
Configuring Client Software Using Remote Notification Us:6219698, Robert Iannucci, Chris Weikart
Robert A Iannucci
No abstract provided.
Computer System For Simulating Physical Processes Using Multiple Integer State Vectors Us:5594671, Hudong Chen, Peter Churchill, Robert Iannucci, Kim Molvig, Gregory Papadopoulos, Stephen Remondi, Christopher Teixeira, Kenneth Traub
Computer System For Simulating Physical Processes Using Multiple Integer State Vectors Us:5594671, Hudong Chen, Peter Churchill, Robert Iannucci, Kim Molvig, Gregory Papadopoulos, Stephen Remondi, Christopher Teixeira, Kenneth Traub
Robert A Iannucci
No abstract provided.
System For Synchronizing Execution By A Processing Element Of Threads Within A Process Using A State Indicator Us:5553305, Robert Iannucci, Steven Gregor
System For Synchronizing Execution By A Processing Element Of Threads Within A Process Using A State Indicator Us:5553305, Robert Iannucci, Steven Gregor
Robert A Iannucci
No abstract provided.
Multithreaded Computer Architecture: A Summary Of The State Of The Art, Robert Iannucci, Guang Gao, Robert Halstead, Burton Smith
Multithreaded Computer Architecture: A Summary Of The State Of The Art, Robert Iannucci, Guang Gao, Robert Halstead, Burton Smith
Robert A Iannucci
No abstract provided.
High Performance Memory System Pct:Ep0199134, Robert Iannucci
High Performance Memory System Pct:Ep0199134, Robert Iannucci
Robert A Iannucci
No abstract provided.
Parallel Machines: Parallel Machine Languages, Robert Iannucci
Parallel Machines: Parallel Machine Languages, Robert Iannucci
Robert A Iannucci
No abstract provided.
Method And Apparatus For Division Pct:Ep0075745, Robert Iannucci, James Kleinsteiber
Method And Apparatus For Division Pct:Ep0075745, Robert Iannucci, James Kleinsteiber
Robert A Iannucci
No abstract provided.
High Performance Memory System Utilizing Pipelining Techniques Us:4685088, Robert Iannucci
High Performance Memory System Utilizing Pipelining Techniques Us:4685088, Robert Iannucci
Robert A Iannucci
No abstract provided.
Method And Apparatus For Division Employing Associative Memory Us:4466077, Robert Iannucci, James Kleinsteiber
Method And Apparatus For Division Employing Associative Memory Us:4466077, Robert Iannucci, James Kleinsteiber
Robert A Iannucci
No abstract provided.