Computer Engineering Commons^™

Reliability-Performance Trade-Offs In Photonic Noc Architectures, Pradheep Khanna Kaliraj

Theses

Advancements in the field of chip fabrication has facilitated in integrating more number of transistors in a given area which lead to the era of multi-core processors. Interconnect became the bottleneck for the multi-core processors as the number of cores in a chip increased. The traditional bus based architectures, which are currently used in the processors, cannot scale up to support the increasing number of cores in a multi-core chip. Hence, Network-on-Chip (NoC) is the preferred communication backbone for modern multicore chips. However, the multi-hop data transmission using wireline interconnects result in high energy dissipation and latency. Hence, many alternative …