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Full-Text Articles in Computer Engineering

Beaglebone Webcam Server, Alexander Corcoran Jun 2012

Beaglebone Webcam Server, Alexander Corcoran

Computer Engineering

The Beaglebone Webcam Server is a Linux based IP webcam, based on an inexpensive ARM development board, which hosts its own web server to display the webcam feed. The server has the ability to either connect to a wired router, or to act as a wireless access point in order for users to connect and control its functions via any Wi-Fi enabled device.


Wireless Sensor Network For Wine Fermentation, Kerry Scharfglass, Andrew Lehmer Jun 2012

Wireless Sensor Network For Wine Fermentation, Kerry Scharfglass, Andrew Lehmer

Computer Engineering

This project implements an automated temperature monitoring system for wine fermentation which is affordable, easy to use, and scalable to typical small winery setups. To realize these requirements, we implemented the system as a wireless sensor network utilizing commercial off-the-shelf hardware. Temperature and system diagnostic information is communicated wirelessly in a peer-to-peer network topology such that all information flows toward an aggregating server. The server makes the temperature information available over the Internet via a web application and alerts the winemaker by email when the temperature has left acceptable bounds that the winemaker may configure. This project also involved materials …


Cuda Web Api Remote Execution Of Cuda Kernels Using Web Services, Massimo J. Becker Jun 2012

Cuda Web Api Remote Execution Of Cuda Kernels Using Web Services, Massimo J. Becker

Master's Theses

Massively parallel programming is an increasingly growing field with the recent introduction of general purpose GPU computing. Modern graphics processors from NVIDIA and AMD have massively parallel architectures that can be used for such applications as 3D rendering, financial analysis, physics simulations, and biomedical analysis. These massively parallel systems are exposed to programmers through in- terfaces such as NVIDIAs CUDA, OpenCL, and Microsofts C++ AMP. These frame- works expose functionality using primarily either C or C++. In order to use these massively parallel frameworks, programs being implemented must be run on machines equipped with massively parallel hardware. These requirements limit …


Check Image Processing: Webp Conversion And Micr Scan Android Application, Trevor Bliss Apr 2012

Check Image Processing: Webp Conversion And Micr Scan Android Application, Trevor Bliss

Computer Engineering

As more users favor smartphones over computers for simple tasks, small businesses are constantly exploring mobile options to present to their customers. This write-up documents an Android application designed for a small company, which allows users to send pictures of checks to the company’s servers for processing. The picture is taken with the devices built-in camera and is converted to Google’s new image format, WebP. The company’s server processes the check and returns the check’s MICR code as a response. This application leverages the Android NDK and JNI to use Google’s open source image conversion libraries as well as socket …


Reactive Routing In Hidra Networks, Scott Michael Marshall Mar 2011

Reactive Routing In Hidra Networks, Scott Michael Marshall

Computer Engineering

In recent years, the Internet has grown so large that the future scalability of the Internet has become a major concern. The two primary scalability concerns are the size of the forwarding table and the ability for BGP to converge while distributing hundreds of thousands of routes.

HIDRA is a new Internet routing architecture that is backwards-compatible with existing routing technologies and protocols that focuses on feasibility-of-implementation. HIDRA remedies the first Internet scalability concern by proposing a means to reduce the number of entries in the default-free zone (DFZ) forwarding table.

This project extends HIDRA by designing a complete reactive …


Asynchronous Mips Processors: Educational Simulations, Robert L. Webb Aug 2010

Asynchronous Mips Processors: Educational Simulations, Robert L. Webb

Master's Theses

The system clock has been omnipresent in most mainstream chip designs. While simplifying many design problems the clock has caused the problems of clock skew, high power consumption, electromagnetic interference, and worst-case performance. In recent years, as the timing constraints of synchronous designs have been squeezed ever tighter, the efficiencies of asynchronous designs have become more attractive. By removing the clock, these issues can be mitigated. How- ever, asynchronous designs are generally more complex and difficult to debug. In this paper I discuss the advantages of asynchronous processors and the specifics of some asynchronous designs, outline the roadblocks to asynchronous …


Wii-Mote Head Tracking: A Three Dimensional Virtual Reality Display, David Fairman Jun 2010

Wii-Mote Head Tracking: A Three Dimensional Virtual Reality Display, David Fairman

Computer Engineering

The goal of this project is to create a customizable three dimensional virtual reality display on a system available to any non-technical user. This System will use the infrared camera component of a standard Nintendo Wii-mote to track a user's head motions in all six major directions. The virtual reality will be a customizable image projected onto a screen or simply shown on a computer or TV monitor. In order to appear 3-dimensional, the image will continually change according to the position of the user's head. As the user moves their head to the left and right, portions of the …


Max Flow Spill Code Placement Algorithm Implemented In Gcc 4.4.3, Stephen Robert Beard Jun 2010

Max Flow Spill Code Placement Algorithm Implemented In Gcc 4.4.3, Stephen Robert Beard

Computer Engineering

The placement of spill code plays an important role in the register allocator of an optimizing compiler. Many computer architectures possess a register linkage convention that dictates which registers are preserved across function calls and which are not. This project addresses the problem of optimizing spill code that is associated with register linkage conventions.

This algorithm was created by Dr. Chris Lupo and is described in the paper Beyond Register Allocation: a Novel Algorithm for Spill-Code Placement. The algorithm was implemented for GCC 2.5.7 for a PA-RISC architecture [4]. The work in this project will involve porting the existing code …


Hidra: Hierarchical Inter-Domain Routing Architecture, Bryan Clevenger May 2010

Hidra: Hierarchical Inter-Domain Routing Architecture, Bryan Clevenger

Master's Theses

As the Internet continues to expand, the global default-free zone (DFZ) forwarding table has begun to grow faster than hardware can economically keep pace with. Various policies are in place to mitigate this growth rate, but current projections indicate policy alone is inadequate. As such, a number of technical solutions have been proposed. This work builds on many of these proposed solutions, and furthers the debate surrounding the resolution to this problem. It discusses several design decisions necessary to any proposed solution, and based on these tradeoffs it proposes a Hierarchical Inter-Domain Routing Architecture - HIDRA, a comprehensive architecture with …


Pretty Lights, Nicholas (Nick) Delmas, Matthew (Matt) Maniaci Apr 2010

Pretty Lights, Nicholas (Nick) Delmas, Matthew (Matt) Maniaci

Computer Engineering

Digital media players often include a visualization component that allows a user to watch a visualization synchronized to their music or videos. This project uses the visualization plugin API of an existing media playback program (WinAmp) but it displays its visuals using physical LED lights. Instead of outputting visuals to the computer screen, data is sent over USB to a micro controller that runs the LED lights. This project aims to give users a more visceral visual experience than traditional visualizations on the computer screen.


A Neural Network Approach To Border Gateway Protocol Peer Failure Detection And Prediction, Cory B. White Dec 2009

A Neural Network Approach To Border Gateway Protocol Peer Failure Detection And Prediction, Cory B. White

Master's Theses

The size and speed of computer networks continue to expand at a rapid pace, as do the corresponding errors, failures, and faults inherent within such extensive networks. This thesis introduces a novel approach to interface Border Gateway Protocol (BGP) computer networks with neural networks to learn the precursor connectivity patterns that emerge prior to a node failure. Details of the design and construction of a framework that utilizes neural networks to learn and monitor BGP connection states as a means of detecting and predicting BGP peer node failure are presented. Moreover, this framework is used to monitor a BGP network …


Store And Forward Routing For Sparse Pico-Satellite Sensor Networks With Data-Mules, Trevor Joseph Koritza Jun 2009

Store And Forward Routing For Sparse Pico-Satellite Sensor Networks With Data-Mules, Trevor Joseph Koritza

Master's Theses

Satellites are playing an increasingly important role in collecting scientific information, providing communication services, and revolutionizing navigation. Until recently satellites were large and very expensive, creating a high barrier to entry that only large corporations and government agencies could overcome. In the past few years the CubeSat project at California Polytechnic University in San Luis Obispo (Cal Poly) has worked to refine the design and launching of small, lightweight, and less expensive satellites called pico-satellites, opening space up to a wider audience. Now that Cal Poly has the launch logistics and hardware under control, a new problem has arisen. These …


Post Register Allocation Spill Code Optimization, Christopher Lupo, Kent Wilken Mar 2006

Post Register Allocation Spill Code Optimization, Christopher Lupo, Kent Wilken

Computer Science and Software Engineering

A highly optimized register allocator should provide an efficient placement of save/restore code for procedures that contain calls. This paper presents a new approach to placing callee-saved save and restore instructions that generalizes Chow's shrink-wrapping technique (Chow 1988). An efficient, profile-guided, hierarchical spill code placement algorithm is used to analyze the structure of a procedure to calculate the minimum dynamic execution count locations to place callee-saved save and restore code. The algorithm is implemented in the Gnu Compiler Collection and has been tested on the SPEC CPU2000 Integer Benchmark suite. Results show that the technique reduces the number of dynamic …