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Full-Text Articles in Engineering
Stochastic Adc Using Digital Standard Cells, Zachary Baltzer
Stochastic Adc Using Digital Standard Cells, Zachary Baltzer
Journal of the Microelectronic Engineering Conference
No abstract provided.
Stochastic Adc Using Standard Cells: Design, Implementation And Eventual Fabrication Of A 4.7-Bit Adc, Zachary Baltzer
Stochastic Adc Using Standard Cells: Design, Implementation And Eventual Fabrication Of A 4.7-Bit Adc, Zachary Baltzer
Journal of the Microelectronic Engineering Conference
As process nodes shrink, analog design increasingly becomes difficult due to space, signal, and noise concerns. With highly synthesized digital design, analog design innovation lags as these specific considerations are to be accounted for. The analog to digital converter, proposed by Weaver et al., is a completely digital design relying on comparator offsets to produce a digital counter that tracks the difference between the input voltage and a reference voltage. To soon be fabricated on GlobalFoundry’s 130 nm CMOS process, the proposed 5-bit ADC uses approximately 90,000 transistors with 1,500 comparators and a full-adder tree consisting of 1,500 adders to …
Design And Fabrication Of Memristors, Tal R. Nagourney
Design And Fabrication Of Memristors, Tal R. Nagourney
Journal of the Microelectronic Engineering Conference
This paper details the design and fabrication of memristors in the RIT Semiconductor and Microsystem Fabrication Laboratory. Two methods of partially oxidizing titanium were explored, reactive sputtering and thermal oxidation. It is determined that thermal oxidation allows for greater control over the oxidation process due to an inability to sufficiently control the gas flow in the sputter chamber. Electron beam lithography is used to define holes in oxide in which the memristors will be fabricated. Due to issues with the lithography, fabrication is incomplete and ongoing.
4-Bit Microprocessor: Design, Simulation, Fabrication, And Testing, A J. Ryan, G O. Phillips, R E. Pearson, L F. Fuller
4-Bit Microprocessor: Design, Simulation, Fabrication, And Testing, A J. Ryan, G O. Phillips, R E. Pearson, L F. Fuller
Journal of the Microelectronic Engineering Conference
The work presented demonstrates the unique ability of Rochester Institute of Technology’s Microelectronic Engineering department to design, simulate, fabricate, and test complex digital integrated circuits. Utilizing the resources available, the author would be the first undergraduate at RIT to successfully drive the creation of a microprocessor from design through fabrication to test. The microprocessor created is the most complex digital circuit ever fabricated at RIT. Fabrication was completed on three lots using the well-established RIT sub μm CMOS Process. Functional CMOS transistors were demonstrated at the Metal 1 level, but complex digital integrated circuits were not realized beyond that.
Design & Fabrication Of An 8 Bit Adc, Garret Phillips
Design & Fabrication Of An 8 Bit Adc, Garret Phillips
Journal of the Microelectronic Engineering Conference
MEMs devices at RIT utilize off chip circuitry to be properly utilized. This paper purposes an eight bit successive approximation analog to digital converter (ADC) to add to said devices as to simplify their operation. The ADC was designed and simulated using Mentor Graphics and Winspice software for the digital and analog components respectively. Lay out was then performed for the device as well as a simplified three bit version and various test circuits. Fabrication was done in the RIT SFML using RIT’s Sub-μ CMOS process, which uses a 2μm gate length. Functional transistors and simple devices …
Design And Fabrication Of Finfets On Soi Substrates, Steven D. Kirby
Design And Fabrication Of Finfets On Soi Substrates, Steven D. Kirby
Journal of the Microelectronic Engineering Conference
A Fin Field Effect Transistor (FinFET) is one of several novel devices that may be used in the future to minimize short channel effects. The FinFET is fabricated on silicon on insulator (SOI) substrate and uses basic integrated circuit processing techniques to obtain a double gate structure. The double gate structure helps to improve subthreshold characteristics and provides low leakage current. The objective of this project was to improve the FinFET device built at RIT. Functioning FinFETs were designed and fabricated previously at RIT. The new design and process changes will help in the understanding of issues found in previous …
Design, Simulation And Fabrication Of Insulated Gate Bipolar Transistors (Igbt), Tejas K. Jhaveri
Design, Simulation And Fabrication Of Insulated Gate Bipolar Transistors (Igbt), Tejas K. Jhaveri
Journal of the Microelectronic Engineering Conference
This project serves as a study to determine the feasibility of the current CMOS toolsets and processes available at Semiconductor & Microsystems Fabrication Laboratory (SMFL) for the fabrication of whole wafer power devices. Several designs and devices were explored. The Insulated Gate Bipolar Transistor (~LGBT) is a device widely used for high power electronic applications and was selected for this study. This device has bipolar current flow and a MOS gate thus combining advantages of both the Double diffused MOS (DMOS) and Power Bipolar junction transistor. Prototypes consisting of transistors with varying densities, gate lengths and gate widths were fabricated …
Design And Fabrication Of Polarization Filter Implementing A Wire Grid Array, Eric Poortinga
Design And Fabrication Of Polarization Filter Implementing A Wire Grid Array, Eric Poortinga
Journal of the Microelectronic Engineering Conference
For decades optical lithography has continually been extended past the conceived limitations of the technology. By optimizing photoresist performance and stepper settings it is possible to image features smaller then the wavelength of light being used to image. This ability allows structures to be designed such that the optical properties of the material change from what would occur at larger scales. One such structure is the wire grid array consisting of parallel metal lines on a quartz substrate. A wire grid array with a period smaller then the wavelength of incident radiation acts as a polarizer. The Incident field perpendicular …
Design, Fabrication, And Testing Of Crystalline Silicon Source/ Drain Finfets, Jesse J. Siman
Design, Fabrication, And Testing Of Crystalline Silicon Source/ Drain Finfets, Jesse J. Siman
Journal of the Microelectronic Engineering Conference
Crystalline silicon source/drain FInFET structures were designed, fabricated, and tested at the RIT Semiconductor & Microsystems Fabrication Laboratory (SMFL). Process development was completed using hand calculations, simulations, and similar processing techniques based upon mature RIT semiconductor manufacturing processes. The design under investigation is a dog-bone structure fabricated on SOT substrates. The crystalline silicon source/drain FinFETs exhibited a field effect behavior for all transistor sizes fabricated, however the smaller 1μm FinFETs were more susceptible to background noise. The smallest device, a 1x2μm FInFET yielded VT=1.53V and a drive current of 510 μA with VG=5V. The largest device, …
Analog Ic Design And Fabrication, James Tom
Analog Ic Design And Fabrication, James Tom
Journal of the Microelectronic Engineering Conference
The purpose of this project was to test the performance of analog integrated circuits and to characterize the MOSFET SPICE parameters. The data that can be obtained from this testing can be helpful for further research in the area of Analog IC design. The Semiconductor & Microsystems Fabrication Laboratory (SMFL) is a constantly evolving facility, with equipment constantly entering and leaving the lab. The process technology used was the RIT Subμ-CMOS Process, a vehicle used to teach students about process integration, semiconductor manufacturing, and the effects of process technology and device operation. Therefore, the Sub-Micron process must adapt to changes …
Design And Fabrication Of A Micromechanical Pressure Sensor, Neal V. Lafferty
Design And Fabrication Of A Micromechanical Pressure Sensor, Neal V. Lafferty
Journal of the Microelectronic Engineering Conference
A Microelectromechanical (MEMS) pressure sensor was designed, fabricated, and tested. Photomasks were designed for the project and built in house at RIT. The masks included designs for three separate device designs: devices to be fabricated with a KOH bulk etch, devices to be fabricated with an Surface Technology Systems (STS) Deep Reactive Ion Etch (DRIE), and a third set of scaled device designs for use with the STS DRIE process. Devices were tested in house, and the ideal design was determined. The most sensitive device, which had a resistor L/W of 10, demonstrated a voltage differential of 39 mV.
Design And Fabrication Of On-Chip Inductors, Robert K. Requa
Design And Fabrication Of On-Chip Inductors, Robert K. Requa
Journal of the Microelectronic Engineering Conference
An inductor is a conductor arranged in an appropriate shape (such as a conducting wire wound as a coil) to supply a certain amount of self-inductance. This passive device stores magnetic energy. Simple spiral planar inductors of varying geometry were designed and fabricated on a silicon substrate insolated by silicon oxide. The process chosen for fabrication of the devices was the copper damascene process. Line widths and spaces varied from 5μm to 20μm. Thickness of the copper wire was approximately 1.5 μm. The inductors were isolated from the silicon substrate by 0.5 μm of Si02 and wires were insolated …
Design And Analysis Of A Cmos Based Mems Accelerometer, Matthew A. Zeleznik
Design And Analysis Of A Cmos Based Mems Accelerometer, Matthew A. Zeleznik
Journal of the Microelectronic Engineering Conference
Traditionally, microelectromechanical systems (MEMS) have been fabricated using standard surface micromachining or bulk micromachining processes with prior or subsequent CMOS incorporation. Recently, a new hybrid technique known as CMOS enicromachining has been developed allowing for parallel fabrication of mechanical and electrical components. A single axis and dual axis accelerometer have been designed for submission for an ASIMPS alpha run using the CMOS micromachining process. Electrical and mechanical analysis and simulations for the single axis accelerometer have been performed. The sensitivity of the single axis accelerometer has been calculated to be 19.66mV/g neglecting the effects of parasitic capacitance. The released die …
Design And Fabrication Of Ring Gate Surface Junction Tunneling Devices, Eliott R. Hughes
Design And Fabrication Of Ring Gate Surface Junction Tunneling Devices, Eliott R. Hughes
Journal of the Microelectronic Engineering Conference
Silicon based ring gate surface junction tunneling devices (SJT) were studied due to their promise of incorporating quantum functional devices with integrated circuits. SJT devices of various gate lengths ranging from 1 μm to 50 μm were designed using Mentor Graphics tools, and were fabricated using standard CMOS processes on S1MOX substrates. SIMOX wafers were used to help reduce bulk leakage and enhance the drain impurity profile. SIMOX mesa isolation also significantly reduced the process flow.
Design And Characterization Of An Optical Proximity Correction (Opc) Mask, Sumir Varma
Design And Characterization Of An Optical Proximity Correction (Opc) Mask, Sumir Varma
Journal of the Microelectronic Engineering Conference
A normal binary chrome mask is designed with optical proximity correction features to test their effect on the lithographic image formed. A significant image improvement is seen due to the addition of the OPC features.
Design And Construction Of A Noncontact Resistivity Measurement Instrument, William R. Hamilton
Design And Construction Of A Noncontact Resistivity Measurement Instrument, William R. Hamilton
Journal of the Microelectronic Engineering Conference
An Eddy—Current Gauge was fabricated from the design of G. L. Miller, D. A. H. Robinson and T. D. Wiley Cl]. The electronics involved was mounted on a printed circuit board and the header assembly was successfully machined and housed in Lucite. The calibration and testing confirmed the instrument’s linear properties for measuring conductivity.
Design, Layout And Realization Of An All Nor Enhancement Type Pmos Serial Adder, Steven M. Macaluso
Design, Layout And Realization Of An All Nor Enhancement Type Pmos Serial Adder, Steven M. Macaluso
Journal of the Microelectronic Engineering Conference
A four bit serial adder was designed with PMOS NOR gates from a truth table that models binary serial addition. Three storaqe reqisters were also included in the desiqn, two-four bit shift registers for the incoming digits and one-five bit register for the sum. A simple five gate latch was used for the bits of these registers. The circuit was layed out using ICE , a software program designed to facilitate circuit layout for mask making at R.I.T.