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Full-Text Articles in Engineering
Evaluating Similarity Of Cross-Architecture Basic Blocks, Elijah L. Meyer
Evaluating Similarity Of Cross-Architecture Basic Blocks, Elijah L. Meyer
Browse all Theses and Dissertations
Vulnerabilities in source code can be compiled for multiple processor architectures and make their way into several different devices. Security researchers frequently have no way to obtain this source code to analyze for vulnerabilities. Therefore, the ability to effectively analyze binary code is essential. Similarity detection is one facet of binary code analysis. Because source code can be compiled for different architectures, the need can arise for detecting code similarity across architectures. This need is especially apparent when analyzing firmware from embedded computing environments such as Internet of Things devices, where the processor architecture is dependent on the product and …
Geo-Spatial Mapping As A Catalyst For Creative And Engaged Design In Engineering Education, Jessie Zarazaga
Geo-Spatial Mapping As A Catalyst For Creative And Engaged Design In Engineering Education, Jessie Zarazaga
Multidisciplinary Studies Theses and Dissertations
Exploiting the technology of geo-spatial mapping student designers can develop deep understandings of the rich and layered data of a spatial context, a situational understanding essential to responsible civic design. However the actions inherent in the construction of spatial data armatures can simultaneously be harnessed as creative strategies, in which mapping processes become the context for generative spatial play. The ambition of this study is to propose efficient pedagogic structures to help prepare civil and environmental student engineers to be not only strong participants, but leaders, in the design of the built environment. The interpretation of site data, mapped as …
A Compiler Target Model For Line Associative Registers, Paul S. Eberhart
A Compiler Target Model For Line Associative Registers, Paul S. Eberhart
Theses and Dissertations--Electrical and Computer Engineering
LARs (Line Associative Registers) are very wide tagged registers, used for both register-wide SWAR (SIMD Within a Register )operations and scalar operations on arbitrary fields. LARs include a large data field, type tags, source addresses, and a dirty bit, which allow them to not only replace both caches and registers in the conventional memory hierarchy, but improve on both their functions. This thesis details a LAR-based architecture, and describes the design of a compiler which can generate code for a LAR-based design. In particular, type conversion, alignment, and register allocation are discussed in detail.
Alternative Mission Concepts For The Exploration Of Outer Planets Using Small Satellite Swarms, Andrew Gene Blocher
Alternative Mission Concepts For The Exploration Of Outer Planets Using Small Satellite Swarms, Andrew Gene Blocher
Master's Theses
Interplanetary space exploration has thus far consisted of single, expensive spacecraft missions. Mission costs are particularly high on missions to the outer planets and while invaluable, finite budgets limit our ability to perform extensive and frequent investigations of the planets. Planetary systems such as Jupiter and Saturn provide extremely complex exploration environments with numerous targets of interest. Exploring these targets in addition to the main planet requires multiple fly-bys and long mission timelines. In LEO, CubeSats have changed the exploration paradigm, offering a fast and low cost alternative to traditional space vehicles. This new mission development philosophy has the potential …
Computational Intelligence Based Complex Adaptive System-Of-Systems Architecture Evolution Strategy, Siddharth Agarwal
Computational Intelligence Based Complex Adaptive System-Of-Systems Architecture Evolution Strategy, Siddharth Agarwal
Doctoral Dissertations
The dynamic planning for a system-of-systems (SoS) is a challenging endeavor. Large scale organizations and operations constantly face challenges to incorporate new systems and upgrade existing systems over a period of time under threats, constrained budget and uncertainty. It is therefore necessary for the program managers to be able to look at the future scenarios and critically assess the impact of technology and stakeholder changes. Managers and engineers are always looking for options that signify affordable acquisition selections and lessen the cycle time for early acquisition and new technology addition. This research helps in analyzing sequential decisions in an evolving …
Characterization Of Green Roofs And Their Potential Effects On The Union College Campus, Cybil Tribie
Characterization Of Green Roofs And Their Potential Effects On The Union College Campus, Cybil Tribie
Honors Theses
A green roof is the construction of protective layers and vegetation on the roof of a building. Green roofs are capable of providing ecological benefits to the environment as well as economic advantages for the client. Therefore, my thesis will explore the characterization features of green roofs by focusing on the layers they are made up of, the different types of green roofs, and the benefits they can provide. Although this technology is relatively new to the United States in comparison to places such as Germany, where green roofs have been extensively used for over 40 years, there is a …
Asynchronous Mips Processors: Educational Simulations, Robert L. Webb
Asynchronous Mips Processors: Educational Simulations, Robert L. Webb
Master's Theses
The system clock has been omnipresent in most mainstream chip designs. While simplifying many design problems the clock has caused the problems of clock skew, high power consumption, electromagnetic interference, and worst-case performance. In recent years, as the timing constraints of synchronous designs have been squeezed ever tighter, the efficiencies of asynchronous designs have become more attractive. By removing the clock, these issues can be mitigated. How- ever, asynchronous designs are generally more complex and difficult to debug. In this paper I discuss the advantages of asynchronous processors and the specifics of some asynchronous designs, outline the roadblocks to asynchronous …
A Field Programmable Gate Array Architecture For Two-Dimensional Partial Reconfiguration, Fei Wang
A Field Programmable Gate Array Architecture For Two-Dimensional Partial Reconfiguration, Fei Wang
Browse all Theses and Dissertations
Reconfigurable machines can accelerate many applications by adapting to their needs through hardware reconfiguration. Partial reconfiguration allows the reconfiguration of a portion of a chip while the rest of the chip is busy working on tasks. Operating system models have been proposed for partially reconfigurable machines to handle the scheduling and placement of tasks. They are called OS4RC in this dissertation. The main goal of this research is to address some problems that come from the gap between OS4RC and existing chip architectures and the gap between OS4RC models and practical applications. Some existing OS4RC models are based on an …