Engineering Commons^™

Neural Network In Hardware, Jiong Si

UNLV Theses, Dissertations, Professional Papers, and Capstones

This dissertation describes the implementation of several neural networks built on a field programmable gate array (FPGA) and used to recognize a handwritten digit dataset – the Modified National Institute of Standards and Technology (MNIST) database. A novel hardwarefriendly activation function called the dynamic ReLU (D-ReLU) function is proposed. This activation function can decrease chip area and power of neural networks when compared to traditional activation functions at no cost to prediction accuracy.

The implementations of three neural networks on FPGA are presented: 2-layer online training fully-connected neural network, 3-layer offline training fully-connected neural network, and two solutions of Super-Skinny …

Time-Difference Circuits: Methodology, Design, And Digital Realization, Shuo Li

Doctoral Dissertations

This thesis presents innovations for a special class of circuits called Time Difference (TD) circuits. We introduce a signal processing methodology with TD signals that alters the target signal from a magnitude perspective to time interval between two time events and systematically organizes the primary TD functions abstracted from existing TD circuits and systems. The TD circuits draw attention from a broad range of application fields. In addition, highly evolved complementary metal-oxide-semiconductor (CMOS) technology suffers from various problems related to voltage and current amplitude signal processing methods. Compared to traditional analog and digital circuits, TD circuits bring several compelling features: …

Adaptive-Hybrid Redundancy For Radiation Hardening, Nicolas S. Hamilton

Theses and Dissertations

An Adaptive-Hybrid Redundancy (AHR) mitigation strategy is proposed to mitigate the effects of Single Event Upset (SEU) and Single Event Transient (SET) radiation effects. AHR is adaptive because it switches between Triple Modular Redundancy (TMR) and Temporal Software Redundancy (TSR). AHR is hybrid because it uses hardware and software redundancy. AHR is demonstrated to run faster than TSR and use less energy than TMR. Furthermore, AHR allows space vehicle designers, mission planners, and operators the flexibility to determine how much time is spent in TMR and TSR. TMR mode provides faster processing at the expense of greater energy usage. TSR …

Statistical Analysis Of A Channel Emulator For Noisy Gradient Descent Low Density Parity Check Decoder, Rakin Muhammad Shadab

All Graduate Theses and Dissertations, Spring 1920 to Summer 2023

The purpose of a channel emulator is to emulate a communication channel in real-life use case scenario. These emulators are often used in the domains of research in digital and wireless communication. One such area is error correction coding, where transmitted data bits over a channel are decoded and corrected to prevent data loss. A channel emulator that does not follow the properties of the channel it is intended to replicate can lead to mistakes while analyzing the performance of an error-correcting decoder. Hence, it is crucial to validate an emulator for a particular communication channel. This work delves into …

Improving The Single Event Effect Response Of Triple Modular Redundancy On Sram Fpgas Through Placement And Routing, Matthew Joel Cannon

Theses and Dissertations

Triple modular redundancy (TMR) with repair is commonly used to improve the reliability of systems. TMR is often employed for circuits implemented on field programmable gate arrays (FPGAs) to mitigate the radiation effects of single event upsets (SEUs). This has proven to be an effective technique by improving a circuit's sensitive cross-section by up to 100x. However, testing has shown that the improvement offered by TMR is limited by upsets in single configuration bits that cause TMR to fail.This work proposes a variety of mitigation techniques that improve the effectiveness of TMR on FPGAs. These mitigation techniques can alter the …

Optimization And Hardware Implementation Of Syba-An Efficient Feature Descriptor, Samuel Gaylin Fuller

Theses and Dissertations

Feature detection, description and matching are crucial steps in many computer vision algorithms. These rely on feature descriptors to be able to match image features across sets of images. This paper discusses a hardware implementation and various optimizations of our lab's previous work on the SYnthetic BAsis feature descriptor (SYBA). Previous work has shown that SYBA can offer superior performance to other binary descriptors, such as BRIEF. This hardware implementation on an FPGA is a high throughput and low latency solution, which is critical for applications such as: high speed object detection and tracking, stereo vision, visual odometry, structure from …

Surface Engineering Solutions For Immersion Phase Change Cooling Of Electronics, Brendon M. Doran

Master's Theses

Micro- and nano-scale surface modifications have been a subject of great interest for enhancing the pool boiling heat transfer performance of immersion cooling systems due to their ability to augment surface area, improve wickability, and increase nucleation site density. However, many of the surface modification technologies that have been previously demonstrated show a lack of evidence concerning scalability for use at an industrial level. In this work, the pool boiling heat transfer performance of nanoporous anodic aluminum oxide (AAO) films, copper oxide (CuO) nanostructure coatings, and 1D roll-molded microfin arrays has been studied. Each of these technologies possess scalability in …

Modernization Of Laboratory Curriculum For The Undergraduate Digital Systems Course, Brolyne H. Onyango

Electrical Engineering Theses

We introduce a novel hybrid approach to modernize the curriculum for the Digital Systems course, using traditional circuit construction, simulation software and implementation of circuits using reconfigurable logic. The NI Multisim circuit simulation software and a Digilent Basys-3 board are utilized. Students will use a breadboard and chips to construct basic combinational circuits using logic gates. Next, they will use the NI Multisim to build and simulate circuits that are difficult to build physically. Finally, an FPGA board will be utilized to implement the most complex circuits. Typically, the use of FPGA technology requires knowledge of HDL, which is considered …

Neutron Beam Testing Methodology And Results For A Complex Programmable Multiprocessor Soc, Jordan Daniel Anderson

Theses and Dissertations

The Xilinx Multiprocessor System-on-Chip (MPSoC) is a complex device that uses 16nm FinFET technology to combine multiple processors, a large amount of FPGA resources, and many I/O interfaces on a single chip die. These features make the MPSoC a high-performance and architecturally flexible device. The potential computing power makes the MPSoC ideal for many embedded applications including terrestrial and space applications. The MPSoC, however, does not have extensive radiation history as many other devices have. The extent of the effect that ionized particles may have on the MPSoC is not well established. To solve this problem, neutron radiation testing can …