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1999

Rochester Institute of Technology

Articles 1 - 16 of 16

Full-Text Articles in Engineering

I-Line Exposure Capability For 6 Inch Wafers, Jerome Wandell Jan 1999

I-Line Exposure Capability For 6 Inch Wafers, Jerome Wandell

Journal of the Microelectronic Engineering Conference

The HIT Factory is currently in the development phase for a 6 inch sub-micron CMOS process. The addition of the Canon FPA-2000i1 stepper completes the necessary equipment required to perform a 6 inch photo process at HiT. The major focus of this project is to further the 6 inch photo process development, specifically to setup the exposure process for the first two levels (p-well and active) of the HIT test chip. TV pre-align mark number 2 and auto-align mark 20P-4F were added to all eleven levels of the HIT test chip layout around the originally designed pattern~ area. The revised …

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Critical Dimension Analysis On The Rit Canon I-Line Stepper, Justin Novak Jan 1999

Critical Dimension Analysis On The Rit Canon I-Line Stepper, Justin Novak

Journal of the Microelectronic Engineering Conference

This project involved the simulation and analysis of critical dimensions (CD) using the RIT Canon 2000i1 i-line stepper. This was accomplished by optimizing the stepper parameters for specific resist feature widths. There are many tools and methods that lithography engineers have at their disposal for use in optimizing current and future lithography processes. The focus-exposure (1?~E) matrix and resulting plot are integral parts of standard IC processing~ It is one of the most important plots used in lithography since it demonstrates how exposure and focus work together to affect critical dimension, sidewall angle, and resist thickness loss data. This data …

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Amorphous Silicon For 157nm Lithography, Carlos Fonseca Jan 1999

Amorphous Silicon For 157nm Lithography, Carlos Fonseca

Journal of the Microelectronic Engineering Conference

Amorphous silicon (a-Si) was investigated as a potential masking material at 157nm wavelength. Characterization of a-Si included film deposition on CaF2 (calcium fluoride) substrates through reactive sputtering, spectroscopic ellipsometry in the UV range, reflection and transmission at 157nm wavelength, and extraction of optical constants (n&k) with a commercial software package. Experimental results suggest that a-Si films deposited at RIT have similar optical constants as published values in the UV range. Simulation work suggests that a 50A silicon nitride film can be used as an anti-reflective layer to minimize reflections at the a-Si I air boundary. Consequently, silicon nitride films were …

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Resist Characterization For 157nm Lithography, Christopher Bolton Jan 1999

Resist Characterization For 157nm Lithography, Christopher Bolton

Journal of the Microelectronic Engineering Conference

A resist characterization experiment was performed utilizing 157nm Vacuum Ultra-violet (VUV) Lithography. A number of older technology resists such as MXP8, APEX-E, and UVIII were placed in the beam path of a Lumonics Series 700 fluorine excimer laser and subjected to timed exposures on the tool. The features were then developed in a low normality CD26 developer and characterization curves for each of the resists were plotted. Through the experimentation it was found that each of the three resists investigated was able to clearly demonstrate imaging qualities at 157nm. The contrast curves of the MXP8 and APEX-E resist indicate that …

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Oxidation Kinetics Of Nitrogen Implanted Silicon, Nathaniel E. Wescott Jan 1999

Oxidation Kinetics Of Nitrogen Implanted Silicon, Nathaniel E. Wescott

Journal of the Microelectronic Engineering Conference

Incorporation of nitrogen into the silicon lattice has been shown to severely retard the oxidation rate. The objective of this experiment was to determine a) whether it was a damage related issue and b) the kinetics. Equal doses of silicon were implanted along with the diatomic nitrogen (AMU 28) to determine whether it was a damage related issue. The added silicon did not hinder or benefit oxide growth. From this experiment, the oxidation rate of nitrogen implanted silicon can be best fit by the use of a linear model. Surface charge analysis indicated that flatband charge, interface trap density, and …

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Plasma Induced Damage To Thin Gate Oxides, Dustin L. Winters Jan 1999

Plasma Induced Damage To Thin Gate Oxides, Dustin L. Winters

Journal of the Microelectronic Engineering Conference

Two mechanisms of plasma processing damage to thin gate oxide structures were studied. Thin 17.5 mu oxide on Si substrate structures were studied after direct exposure to a oxygen plasma environment with surface charge analysis and breakdown voltage measurements. A second antenna structure was used to study the charging effects of an oxygen plasma on 17.5 nm gate oxides through breakdown voltage measurements. A correlation was found between duration of plasma exposure and the extent of damage in terms of decreased dielectric strength and changes in oxide charge levels for both experiments.

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Oxide Passivated Nanocrystalline Silicon Trap-Controlled Memory Devices, Burcay Gurcan Jan 1999

Oxide Passivated Nanocrystalline Silicon Trap-Controlled Memory Devices, Burcay Gurcan

Journal of the Microelectronic Engineering Conference

An alternative to the single floating gate on a standard EEPROM device could be a continuous semi insulating layer in which the distribution of charge can be controlled. By partial oxidation of porous silicon, a new material named Oxide Passivated Nanocrystalline Silicon (OPNSi) is formed, which has embedded Si nanocrystals in a porous glass structure. With oxide barriers between silicon nanocrystals, carriers can be confined to the silicon crystallites or trapped at interface states on the surface of these nanocrystals. With the assistance of an electric field, carriers can undergo direct tunneling through the very thin barriers and alter the …

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Integration Of Sige Resonant Interband Tunneling Diodes With Rit Cmos, Petya Vachranukunkiet Jan 1999

Integration Of Sige Resonant Interband Tunneling Diodes With Rit Cmos, Petya Vachranukunkiet

Journal of the Microelectronic Engineering Conference

This study investigates the integration of SiGe resonant interband tunneling diodes (RTD) with a standard silicon p-well CMOS process. It is feasible to build the RTD devices on the MOS source/drain regions if the RTD process did not degrade MOS devices. Besides, some etch selectivity issues need to be addressed. MOS transistors were subjected to the thermal cycling of the molecular beam epitaxial growth process and the rapid thermal anneal used in the fabrication of RTDs prior to contact formation. No destructive effects on the operation of NMOS and PMOS devices were observed. NMOS devices exhibited a positive shift of …

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Development Of An Anisotropic, Highly Selective Tungsten Silicide Dry Etch Process, Thomas Schulte Jan 1999

Development Of An Anisotropic, Highly Selective Tungsten Silicide Dry Etch Process, Thomas Schulte

Journal of the Microelectronic Engineering Conference

The development of an anisotopic Tungsten Suicide etch that will provide good selectivity to photoresist as well as an underlying oxide has been studied. It has been found that by reducing the amount of fluorine (SF6) in the system and increasing the chlorine concentration, slightly tapered sidewalls can be achieved without the use of a polymer forming gas. An optimum process was developed on an Applied Materials P-5000 MxP system. A condition of 10 sccm SF6, 40 sccm Cl2, 20 sccm 11e02 at 30 mTorr, and 400W presents slightly tapered sidewalls with within wafer uniformity of 4.85%. The selectivity of …

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Electrolytic Plating Of Copper For Advanced Interconnects, Michael T. Myszka Jan 1999

Electrolytic Plating Of Copper For Advanced Interconnects, Michael T. Myszka

Journal of the Microelectronic Engineering Conference

There is great interest in the semiconductor industry to move to copper for advanced interconnect processing. The purpose of this study was to develop an electroplating process so further studies in copper processing can be undertaken at R.LT. Electroplating was performed using the facilities available at the University of Rochester. This system utilizes a copper sulfate based electrolyte and an 8” wafer holder. In order to use the electroplating tool for four-inch wafers, a fixture was designed. Plating was performed on Si wafers coated with adhesion and seed layer of copper at varying current densities. Plated films were characterized for …

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Pattern Density Effects On The Chemical Mechanical Planarization Of An Interlevel Polymer Dielectric, Teresa M. Evans Jan 1999

Pattern Density Effects On The Chemical Mechanical Planarization Of An Interlevel Polymer Dielectric, Teresa M. Evans

Journal of the Microelectronic Engineering Conference

Chemical Mechanical Planarization is quickly becoming a standard in microelectronical processing. CMP can decrease the depth of focus constraints in photolithography, resolve topography issues for multilevel interconnects, improve metal step coverage, and be used as an alternative etch process. The recent break-through in the copper damascene process has invoked a large number of studies focused on the planarization of oxides and metals. The research has proven beneficial for other applications where oxides are used as an interlevel dielectric material It has also shown the need for further studies in the polishing of other dielectric materials. The purpose of this experiment …

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8 Bit Analog-To-Digital Converter Design And Simulation, Alberto J. Reyes Jan 1999

8 Bit Analog-To-Digital Converter Design And Simulation, Alberto J. Reyes

Journal of the Microelectronic Engineering Conference

The purpose of this study is to present and characterize an 8 bit AD converter implemented with flash architecture. Flash architecture provides with one of the fastest and easiest ways to convert analog input signals to digital outputs. Analog-to-digital conversion is the process in which a continuously varying analog signal is transformed into a multilevel digital signal. Analogue electrical waveforms are applied to the converter and are sampled at a fixed rate. Sample values are then expressed as a binary number consisting of 0’s and l’s. The resulting digital code can be used to encode digital audio, applications in video …

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Fabrication And Development Of A Charge Injection Device Imager, Ivan Puchades Jan 1999

Fabrication And Development Of A Charge Injection Device Imager, Ivan Puchades

Journal of the Microelectronic Engineering Conference

As Rochester Institute of Technology (RH) brings into production i-line capabilities with a new Canon stepper, resolution beyond 2μm will be possible. The present project prepares one of RIT’s most novel and successful processes for this transition. The process for a Charge Injection Device Imager (CD)) has been entirely developed at RIT through the work and collaboration between the Imaging Science and Microelectronic Engineering Departments. After the initial success in the design and fabrication of 8X8 and 32X32 imager, a more challenging 54X40 process was developed employing 6-micron PMOS technology. The goal of this project is the successful …

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Oxide Passivated Nanocrystalline Silicon Led Optimization, Tina M. Wheaton Jan 1999

Oxide Passivated Nanocrystalline Silicon Led Optimization, Tina M. Wheaton

Journal of the Microelectronic Engineering Conference

The objective of this project was to create an optimized, repeatable process for integrated PSI (Porous Silicon) LEDs. Porous Silicon is a lightemitting version of silicon, formed by electrochemical etching in an HF-containing solution. This material becomes stable once passivated with oxygen at high temperatures (900°C) and maintains its light-emitting properties. This study systematicaUy investigated the process effects on electroluminescence (EL) and electrical transport characteristics. The relationship between fabrication conditions and the structural and electronic properties of porous silicon have been subsequently examined. It was discovered that pre anodization substrate preparation had a dominant influence on the device characteristics. Analysis …

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Investigation Of A Silicon Bulk Etched Incandescent Light Source, Keith A. Roehner Jan 1999

Investigation Of A Silicon Bulk Etched Incandescent Light Source, Keith A. Roehner

Journal of the Microelectronic Engineering Conference

An attempt of fabricating an incandescent light source was made at Rochester Institute of Technology. Filament length, width, material and shape as well as encapsulation method were under investigation in the experiment. Due to a design flaw, the devices could not be tested for functionality. This has since been fixed and another attempt will be made to fabricate the devices.

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Silicon Based Light Emission By Avalanche Breakdown Of Shallow P+/N+ Junctions, Peter I. Ritchie Jan 1999

Silicon Based Light Emission By Avalanche Breakdown Of Shallow P+/N+ Junctions, Peter I. Ritchie

Journal of the Microelectronic Engineering Conference

The objective of this study was to develop and demonstrate a technology for producing optical signals on a VLSI chip using only standard silicon processing techniques. The design of the process requires shallow p+/n+ junctions to minimize the high absorption inherent in silicon for λ< 8SOnm and to obtain low reversed biased voltages for avalanche break down of the p+/n+junction due to impact-ionization. The effects of doping and device geometry on the visible luminescence of reverse biased Si p+In+ junction diodes has been investigated. Each diode designed has a unique design incorporating sharp edges that promote high fields that aid the onset of break down. The p+ doping was varied while other processing parameters were held constant. All vertical junction diodes had excellent diode characteristics but no light emission was observed. Lateral junction diodes had typical reverse breakdown voltages of between 6 and 7 volts while certain devices of set geometry broke down rather sharply at 4 volts with light emission. Intensity and breakdown characteristics seemed to correlate with magnitude of p+ dose and device geometry.

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