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Articles 1 - 30 of 32
Full-Text Articles in Engineering
Multilevel Metalization, Michael J. Bailey
Multilevel Metalization, Michael J. Bailey
Journal of the Microelectronic Engineering Conference
A bilevel metallization process using aluminum with 1~ silicon for the Metal 1 layer, pure aluminum for the Metal 2 layer, and Accuglass X-11 311 Series spin-on glass for the interlevel dielectric was investigated. Problems encountered in via etching with previous bilevel work were eliminated by using a modified buffered HF etchant. Vias down to 6x6um in size were found to conduct and have resistances less than 1 Ohm. Spin-on glass coating processes, however, were still in need of refinement, as numerous pinholes were observed over the aluminum regions.
A Comparison Between Resist Hardening Using A Conformable Mold And Plasma Resist Image Stabilization: Techniques To Enhance Resist Thermal Stability, Kathleen M. Brown
A Comparison Between Resist Hardening Using A Conformable Mold And Plasma Resist Image Stabilization: Techniques To Enhance Resist Thermal Stability, Kathleen M. Brown
Journal of the Microelectronic Engineering Conference
KTI-820, a positive photoresist was hardened utilizing two different methods. The PRIST technique involved the exposure of the patterned resist to a plasma containing CF4 plus Helium followed by a 210C, 30 mm postbake. The RHCM technique involved the encapsulation of the patterned resist with a PMMA mold followed by a 210C, 30 mm postbake and subsequent PMMA removal. The performance of hardened structures on multilayer substrates was investigated for both dry etching and ion implantation processes. The results indicate that the RHCM technique is the superior method. Scanning electron micrographs showed a minimum amount of pattern distortion while nanoline …
Design Of A 4-Bit Microprocessor, Hsiao-Hui Miguel Chen
Design Of A 4-Bit Microprocessor, Hsiao-Hui Miguel Chen
Journal of the Microelectronic Engineering Conference
A four bit microprocessor’s layout was drawn on an Apollo workstation using MOSIS two lambda design rules. The layout’s operation was verified by breadboarding with 74’00 HCMOS logic parts during Spring Quarter 1990 by Theodore D’Antonoli. Based on his findings, the layout was revised and several design changes were added. At the same time, a software simulation program (uPROSIM) for the processor was written in FORTRAN on the RIT VMS Computer System.
Design And Fabrication Of Five Microns Nmos Sram, Robert Chizmadia
Design And Fabrication Of Five Microns Nmos Sram, Robert Chizmadia
Journal of the Microelectronic Engineering Conference
A 126 bit by one bit NMDS static RAM was designed following design rules for RIT’s standard four layer NMDS process. Verification of working devices was done using the SPICE circuit simulator, but some concerns exist with this because of assumptions made in model parameters. Fabrication was an intended goal of this project, but time restraints allowed only masks to be made.
An Ellipsometeric Evaluation Of Ion Implanted Silicon, Patrick G. Drennan
An Ellipsometeric Evaluation Of Ion Implanted Silicon, Patrick G. Drennan
Journal of the Microelectronic Engineering Conference
~ Split Split Plot Design was implemented to investigate the relationship between the ion implantation conditions and the complex refractive index of the inherent damage layer. Four factors chosen to evaluate this relationship were wafer orientation, dose concentration, implant acceleration potential, and screen oxide thickness. The response variable was the complex refractive index of the damaged layer measured by ellipsometry. Results indicate that there is a relationship between the dose concentration and the response variable that is most sensitive to doses between 5e13 ions/cm2 and 5e15 ions/cm2. However, the range of the refractive index increases considerably in this range to …
Energy Dispersive Spectroscopy X-Ray Microanalysis, Jim Eun
Energy Dispersive Spectroscopy X-Ray Microanalysis, Jim Eun
Journal of the Microelectronic Engineering Conference
An overview or Energy Dispersive Spectroscopy (EDS) X-ray microanalysis is presented with attention to artifacts present in the X—ray spectrum, such as the Bremsstrahlung, sum peaks, and silicon escape peaks. Sample spectra obtained from Al on Si, Cu on 51, and PZT ferroelectric films demonstrated the capability of obtaining qualitative elemental composition. The elemental spatial distribution, or the X—ray mapping. capability was also demonstrated utilizing a special alloy sample.
Integration Of Cad Data Transcription For E-Beam Lithography, Ian David Fink
Integration Of Cad Data Transcription For E-Beam Lithography, Ian David Fink
Journal of the Microelectronic Engineering Conference
A software system for preparing data for e-beam mask making called Computer Aided Transcription Software is described. In order to appreciate its capabilities, an overview of writing requirements for a MEBES I e-beam tool are given. Sample files and software output are provided to illustrate the concepts.
A Drm Study Of Microposit Sal603 Resist In Developers Of Different Normality, Kimberly A. Guggemos
A Drm Study Of Microposit Sal603 Resist In Developers Of Different Normality, Kimberly A. Guggemos
Journal of the Microelectronic Engineering Conference
Microposit SAL6O3, a negative working chemically amplified electron beam resist, was studied for four developers of different normality: Microposit MF322 (0.266 N), MF321 (0.210 N), MF320 (0.255 N), or MF319 (0.237 N). Wafers were exposed to create eight regions, each with incrementally increasing exposure. Development in each of the eight zones was monitored simultaneously with a Perkin Elmer 5900 Development Rate Monitor (DRM). Increased developer normality was shown to increase development rate and photoresist contrast, but decreased sensitivity.
Characterization And Process Development For The Mebes I Electron Beam Lithography System, Richard D. Holscher
Characterization And Process Development For The Mebes I Electron Beam Lithography System, Richard D. Holscher
Journal of the Microelectronic Engineering Conference
Characterization of a MEBES I electron beam lithography tool was done to investigate electron bear writing errors induced by electrical and mechanical interactions of the system. Process development of SAL6O3 a negatively working chemically amplified resist, which is required to provide a high sensitivity repeatable resist film, was also done.
Evaluation Of A Double Resist Process, Joseph Jech Jr
Evaluation Of A Double Resist Process, Joseph Jech Jr
Journal of the Microelectronic Engineering Conference
A hierarchical analysis of variance was executed on both critical dimension and film thickness data to prove manufacturability of a double layer resist process as compared to an existing device process. Testing was designed to provide estimates of variance on a die—to—die, wafer—to— wafer, and run-to—run basis. Ion implant mask sidewall angle and process repeatability were other concerns investigated. The double resist process displayed improvement in all phases of the process examined except the run—to— run variance of the polysilicon film thickness. More testing is required to determine if the possible cause was related to the process or some outside …
Fully Recessed Oxide Isolation Technology For Nmos Fabrication, Ronald G. Jones Jr
Fully Recessed Oxide Isolation Technology For Nmos Fabrication, Ronald G. Jones Jr
Journal of the Microelectronic Engineering Conference
Fully Recessed Oxide Isolation Technology (FROIT) and LOCOS methods were both fabricated to verify if the FROIT process provides solutions to two major problems associated with LOCOS, namely the bird’s beak formation and surface topography. The FROIT process uses a two step field oxidation and employs a nitride sidewall to recess the oxide and reduce the bird's beak, respectively. The SEM results verified the FROIT process achieved the desired results.
Alignment Error Characterization Using Electrical Probing Techniques, Jeffrey D. Kosa
Alignment Error Characterization Using Electrical Probing Techniques, Jeffrey D. Kosa
Journal of the Microelectronic Engineering Conference
A technique for electrically measuring alignment errors is described and employed to characterize a GCA 4800 DSW stepper. The experimental accuracy was determined to be +I~ 0.05 microns for all line-width measurements. The GCA 4800 stepper’s day - to - day performance was determined to fluctuate between 0 and -1 micron in X and between 0 and +2 microns in Y. Average alignment ranges of +/- 0.74 and +/-0.95 microns in X and Y were ob served across four samples during the wafer-to-wafer variation testing within one run. These errors were directly related to the accuracy of the “pass-shift” values …
Evaluation Of Polyoxide Capacitor Edge Effects Using Ramped I-V Measurements, Loren C. Krott
Evaluation Of Polyoxide Capacitor Edge Effects Using Ramped I-V Measurements, Loren C. Krott
Journal of the Microelectronic Engineering Conference
Thermally grown oxide on poly silicon has poorer insulator properties than an oxide grown on single crystal silicon. Due to surface roughness of the polysilicon surface the localized oxide electric field is enhanced at the surface bumps and asperities. In order to minimize surface roughness attention has to be given to the poly silicon surface for the steps following deposition. This includes doping and annealing the polysilicon in order to increase the grain size and using care in cleaning the poly and growing the oxide. By minimizing the surface roughness the poly oxide has better insulating properties due to a …
Fabrication Of T-Gate Structures Using Double Layer E-Beam Lithography, Eric A. Lehner
Fabrication Of T-Gate Structures Using Double Layer E-Beam Lithography, Eric A. Lehner
Journal of the Microelectronic Engineering Conference
The fabrication of T-gate structures using a bilayer resist scheme of PMMA 495K molecular weight (4% solids) and PMMA 950K molecular weight (3~ solids) for use with electron beam exposure was investigated. The 1.18 sensitivity ratio between these resists was found to be insufficient to adequately provide the resist cavity necessary for fabrication of T-gate aluminum structures.
Local Stress Field Determination For Thin Polysilicon Films, Pirouz Maghsoudnia
Local Stress Field Determination For Thin Polysilicon Films, Pirouz Maghsoudnia
Journal of the Microelectronic Engineering Conference
Local stress field determination by means of free standing structures was investigated. The process for manufacturing these structures was developed and used to study the stress in polysilicon films.. For a 1.5um polysilicon film, the stress was determined to be less than 6.77e8Dynes/cm2. For a 0.5um polysilicon films, the stress was found to be 4. O9e8Dynes/cm2.
Fabrication Of Micromechanical Devices: Pin Joints, Sliders, Springs, And Micromotors, Matthew P. Matessa
Fabrication Of Micromechanical Devices: Pin Joints, Sliders, Springs, And Micromotors, Matthew P. Matessa
Journal of the Microelectronic Engineering Conference
Movable pin Joints, springs, sliders and Rotors have been constructed using silicon fabrication technology. The movable mechanical elements are built using sacrificial layers that are later removed to allow translation and rotation of the structures [1]. The devices obtained physical movement and the rotors of the Rotors spun with compressed air, but electrical rotation of the motors was not accomplished.
Solar Cell Design Employing A Textured Surface, Diane M. Mauersberg
Solar Cell Design Employing A Textured Surface, Diane M. Mauersberg
Journal of the Microelectronic Engineering Conference
Planar-junction, 1 mm x 1 mm, p+/n/n+ silicon solar cells, both with and without a textured surface, were fabricated in order to study the effects of decreased surface reflectance on cell efficiency. The texturing process was performed through the use of a KOH preferential etchant and an array of 10um x 10um windows to form an oxide masking layer. Inverted pyramids etched to points with final base widths being 13.7 microns due to undercutting of the masking oxide. Completed cells, evaluated at an irradiance of 100 mW/cm2, showed greater efficiences for the textured surface, but outputs of both were limited …
Determination Of Si02 Profiles Achievable With Rie Using C2f6 And Chf3, Daniel P. Morvay
Determination Of Si02 Profiles Achievable With Rie Using C2f6 And Chf3, Daniel P. Morvay
Journal of the Microelectronic Engineering Conference
A dry etch S1O2 process was optimized using the Plasmatrac 2406 RIE etcher at RIT, while maintaining selectivity to polysilicon and photoresist. The optimized process had Power of 350 Watts, Pressure of 127 mTorr, C2F6 of 60 sccm, and CHF3 of 171 sccm; This provided an oxide to poly selectivity of 5.5:1 with an oxide slope of 60°.
Bicmos Vs Cmos At Rit, Anatole Raif
Bicmos Vs Cmos At Rit, Anatole Raif
Journal of the Microelectronic Engineering Conference
This project involved the performance comparison of the standard RIT N-well CMOS and a proposed BiCMOS processes. Device parameters were extracted from TMA SUPREM-3 simulations and used to create NPN, PMOS, and NMOS model cards for ~ccusim simulations. Two inverter circuits, one in CMOS and one in BiCMOS were designed to drive a 5OpF load. The BiCMOS circuit was determined to be four times faster, less temperature dependent, and considerably smaller than its CMOS counterpart. These results lead to a final conclusion favoring the development and use of BiCMOS here at RIT.
Linear Poly Gate Charge Coupled Device Imaging Arrays, Lucien Randazzese
Linear Poly Gate Charge Coupled Device Imaging Arrays, Lucien Randazzese
Journal of the Microelectronic Engineering Conference
A five cask level process was used to fabricate single level, poly gated charge coupled devices intended for use as optical imagers. Three micron gate spacing was achieved with an emulsion cask through tight control of the lithography process. Testing revealed a short between the gates. It is hypothysised to result from insufficient poly gate etching or over diffusion of the gate.
Studies Of Optical Lithographic Process With The Aid Of Prolith/2, Wai-Man Wilma Shiao
Studies Of Optical Lithographic Process With The Aid Of Prolith/2, Wai-Man Wilma Shiao
Journal of the Microelectronic Engineering Conference
PROLITH/2, a tool for modelling and analyzing photolithographic processes, was used to explore two statistically designed experiments. The first was the aerial image formation and the second was resist development process. Results are presented to illustrate the software capability.
Polysilicon Emitter Bipolar Transistors, Todd C. Sieger
Polysilicon Emitter Bipolar Transistors, Todd C. Sieger
Journal of the Microelectronic Engineering Conference
Polysilicon emitter vertical NPN transistors were fabricated in an attempt to create devices with very high current gains and high forward Early voltages. TMA SUPREM-3 simulations were used to optimize the process to obtain emitter junction depths of 0.05 and 0.08um. Final emitter junction depths of 0.1um, or less, were measured. High current gains were not achieved, due to high base doping.
Characterization, Optimization, And Qualification Of Shipley 812 Photoresist For Wafertrac Processing, David H. Taylor
Characterization, Optimization, And Qualification Of Shipley 812 Photoresist For Wafertrac Processing, David H. Taylor
Journal of the Microelectronic Engineering Conference
Wafertrac processing was used to optimize the photolithographic process of Shipley 812 positive photoresist. For two, three, four, and five micron lines, it was found that optimum conditions are 30-40 seconds development time in MF-3 19 and about 72 mj/cm2 exposure dose. These optimum conditions maximize the control over the size of the image being replicated into the resist from the mask. Hardbaking of the resist resulted in a 300-400 micron thickness loss as well as a rounding of the resist profile. Contrast varied from 1.42 to 1.76 with the highest contrast being in the optimum development time range of …
Bipolar Device Fabrication Using Rit's Cmos Technology To Develop A Bicmos Process, Luigi Ternullo Jr
Bipolar Device Fabrication Using Rit's Cmos Technology To Develop A Bicmos Process, Luigi Ternullo Jr
Journal of the Microelectronic Engineering Conference
An NPN bipolar transistor process was designed and fabricated for incorporation with RIT’s N well CMOS technology to develop BiCMOS devices. The only additions to the CMOS process were the base masking step, base implant, and drive. Base dose was varied to achieve current gains of 50, 100, and 200 using SUPREM-3. Unfortunately, do to an incomplete etch of the collector region, a rework had to be performed, whose added temperature steps pushed the emitter through the base.
Affects Of Carbon Dioxide And Helium On Reactive Ion Etching Of Silicon Dioxide, Eric E. Thompson
Affects Of Carbon Dioxide And Helium On Reactive Ion Etching Of Silicon Dioxide, Eric E. Thompson
Journal of the Microelectronic Engineering Conference
A study of the etch characteristics of a thermally grown silicon dioxide etch in RITEs 2406 PLASMATRAC RIE was performed for a C2F6 / CHF3 / C02 gas mixture. Correlations between the amount of CHF3 and C02 introduced and Si02 etch rates and selectivity to polysilicon were investigated using a statistical experimental design. Si02 etch rates as high as 1018 A/mm were achieved with a corresponding selectivity to polysilicon of 2.84:1. At a gas flow of 60 sccm C2F6, 171 sccm CHF3, 48 sccm C02, 255 watts & 150 mtorr, an optimized etch for selectivity was found to give an …
Ferroelectric Thin Film Research At Rit, John P. Verostek
Ferroelectric Thin Film Research At Rit, John P. Verostek
Journal of the Microelectronic Engineering Conference
At RIT, a sol-gel method is being used to synthesize lead zirconate titanate (PZT). Techniques available to characterize these films include scanning electron microscopy ellipsometry, energy dispersive analysis using X-rays (EDAX), and X-ray diffraction (XRD) to determine crystallinity. After heating above the Curie temperature, XRD indicated that a perovskite structure, known to be ferroelectric, was obtained for a PZT film.
Characterization Of Chemically Amplified Advanced Negative Resist For G Line Application, Shu Tsai Wang
Characterization Of Chemically Amplified Advanced Negative Resist For G Line Application, Shu Tsai Wang
Journal of the Microelectronic Engineering Conference
Chemically Amplified Advanced Negative Resist for G line application was evaluated under three different Post Exposure Bake temperatures. The photospeed increased from 22mj/cm*2 to lOmj/cm*2 as the post exposure bake temperature was increased from 120C to 140C. A contrast of approximately 2.0 was obtained for all three treatments, as opposed to the expected value of 4.0. The Optical evaluation of line and space. patterns suggested the 120C post exposure bake temperature will give wider exposure process latitude than 130C or 140C temperatures. The resist exhibited high sensitivity below 3Omj/cm*2 with wide exposure process latitude around 2Omj/cm*2.
Development Of A Deep Trench Rie Etch For Capacitor And Isolation Technologies, Joseph W. Wiseman
Development Of A Deep Trench Rie Etch For Capacitor And Isolation Technologies, Joseph W. Wiseman
Journal of the Microelectronic Engineering Conference
A silicon trench 2um deep was etched in a PlasmaTherm 2406 RIE tool using an SF6/C02 chemistry with an oxide mask. The single crystal silicon etch rate was 1100A/min, with a high selectivity to oxide. A trench slope approximately 50 degrees was obtained, with no undercut of the oxide mask.
Design And Fabrication Of A Lateral Bipolar Pnp Transistor Compatible With Rit's Double Diffused Process, James A. Will Ii
Design And Fabrication Of A Lateral Bipolar Pnp Transistor Compatible With Rit's Double Diffused Process, James A. Will Ii
Journal of the Microelectronic Engineering Conference
A chip was designed containing lateral bipolar PNP devices with base widths ranging from four to ten microns. Vertical NPN devices were included in the designs. The transistors were fabricated using a double diffused process employing solid sources. Two different boron collector/emitter predepositions were performed in order to study the effects of the p-type diffusion sheet resistance on both lateral PNP and vertical NPN devices. Testing of the lateral PNP devices shows very small Early voltages for the five and six micron designs, while the four micron design exhibits punchthrough.
Low Temperature Deposition Of Si02 Films By Ecr, Merle D. Yoder Jr
Low Temperature Deposition Of Si02 Films By Ecr, Merle D. Yoder Jr
Journal of the Microelectronic Engineering Conference
SiO films of high quality have been deposited by Electron Cyclotron Resonance (ECR) at temperatures less than 400 ° C. Chemistries of 02 and 25 % SiHqin Ar were used. Deposition rates of about 220 A/minute were obtained, studying films of typical thicknesses of 1100 A. Characteristics of the films studied include refractive index of 1.467 — 1.477, dielectric strengths of 5.0 — 9.0 MV/cm, dielectric constants of 3.8 — 4.2, and buffered HF etch rates of 19 - 21 A/second. These characteristics were shown to degrade around a deposition temperature of 200 °C, with temperatures on either side of …