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Articles 1 - 30 of 37
Full-Text Articles in Engineering
30th Rocky Mountain Conference
30th Rocky Mountain Conference
Rocky Mountain Conference on Magnetic Resonance
Program and abstracts from the 30th annual meeting of the Rocky Mountain Conference, co-sponsored by the Rocky Mountain Section of the Society for Applied Spectroscopy and the Rocky Mountain Chromatography Discussion Group. Held in Denver, Colorado, July 31 - August 5, 1988.
Radiation Effects On Pmos Devices, Camille G. Bates
Radiation Effects On Pmos Devices, Camille G. Bates
Journal of the Microelectronic Engineering Conference
A Cesium—137 gamma radiation source was used to irradiate PMOS capacitors and transistors with doses of 7.50E4, 1.50E5, 3.0E5. The devices were tested for C-V and I-V data before and after irradiation. Results show that all doses created changes in the electrical characteristics, however comparison to literature was I inconclusive.
Boron Solid Source Characterization, Kelly Baycura
Boron Solid Source Characterization, Kelly Baycura
Journal of the Microelectronic Engineering Conference
Standard Oil’s BN—975 planar diffusion sources were used to fabricate integrated resistors. Dopant transfer was done in a N2:02:H2 ambient at 975 C. Two methods of removing the crystal defect layer formed at the surface, low temperature oxidation (LTO) and a nitric acid soak, were evaluated. Successful layer removal was achieved with the LTO. The nitric acid soak met with limited success.
Design Of A Four-Bit Microprocessor A.L.U Using Pmos 10-Um Metal Gate Technology, John F. Bonaker
Design Of A Four-Bit Microprocessor A.L.U Using Pmos 10-Um Metal Gate Technology, John F. Bonaker
Journal of the Microelectronic Engineering Conference
A four-bit ALU chip based on a metal gate PMOS process and 10-urn minimum geometries was designed. The operations performed by the ALU included ADD w/carry, SUBTRACT(2’s complement), INCREMENT, DECREMENT, and the logic functions AND, OR, XOR, and COMPLEMENT. Due to space limitations no data or shift registers were included on the chip. PMOS NOR gates and inverters were used in the hardware Implementation of the logic design. The ALU chip was laid out by using the ICE (Integrated Circuit Editor) design tool.
Cmos Pla Layout Generation, Christopher D. Bryant
Cmos Pla Layout Generation, Christopher D. Bryant
Journal of the Microelectronic Engineering Conference
A dynamic AND - dynamic OR type of PLA was designed using a CMOS process and the layout was done on a CALMA system using l.5um design rules. A PLA with 200 transistors was completed and can be used to perform desired logic functions.
A Method To Improve Step Coverage Of Conventional Positive Working Photoresist, Dave Brzozowy
A Method To Improve Step Coverage Of Conventional Positive Working Photoresist, Dave Brzozowy
Journal of the Microelectronic Engineering Conference
Positive resist coated wafers were Immersed in a dilute alkaline base developer, such as 5:1 AZ351, for a short period of time prior to exposure. The purpose of this sequence was to improve development rate discrimination of conventional positive photoresist, which will enhance step coverage. A SEM comparison of a 5 mIcron line/space pair pattern of AZ13SO resist on a 1.2 micron step, showed this pre-treatment yields improved step coverage compared to a conventional process.
Multilevel Metallization At Rit, Manuel N. Carneiro
Multilevel Metallization At Rit, Manuel N. Carneiro
Journal of the Microelectronic Engineering Conference
This project was a preliminary study of an aluminum/dielectric/aluminum multilayer metallizatiOn scheme. Polyimide and spin on glass were compared using high frequency CV analysis on fabricated capacitors. The simple processing involved showed that good crack-free and adhesive fil s could be formed with both materials although the polyimide was the more ideal CV characteristics. Test masks were generated to measure via resistance and dielectric breakdown in a bi-level structure. The Spin on Glass processing was unsuccessful because of underetching of vias. The polyimide processing was successful displaying good breakdown characteristics but high via resistances.
Automated Design Rule Checking, Carl E. Conrad
Automated Design Rule Checking, Carl E. Conrad
Journal of the Microelectronic Engineering Conference
A Fortran Coded Design Rule Checker was written to analyze the output file of the RIT Integrated Circuit Editor (ICE) program. The design rules for the RIT 4LEVELPMOS process have been successfully implemented for a die size of 1900 by 1900 square micrometers.
Determination Of Minority Carrier Lifetimes Using The Capacitance-Time Technique, Patrick M. Denero
Determination Of Minority Carrier Lifetimes Using The Capacitance-Time Technique, Patrick M. Denero
Journal of the Microelectronic Engineering Conference
Capacitance—Time (C—T) plots were generated using a Micromanipulator model 410 CV system with a Yokogawa 3022 A4 x—Y recorder (with time base activated). MOS capacitors were pulsed instantaneously from accumulation into deep—depletion. The capacitance was then recorded as the samples relaxed back to their equilibrium state (Cmin). The method used to analyze the C—T data was known as a ZERBST analysis. A FORTRAN program was created to handle the differentiating required for the ZERBST plot. Preliminary results indicate that this set—up will accurately determine minority carrier lifetimes.
Response Surface Methodology Using Experimental Design, Jamshed H. Dubash
Response Surface Methodology Using Experimental Design, Jamshed H. Dubash
Journal of the Microelectronic Engineering Conference
A Central—Composite Full Factorial design was performed in aiming to optimize the develop and bake processes on KTI 820 resist and KTI 934 developer using the GCA Wafertrac. The responses looked at were critical dimension and resist thickness after development with the independent variables of postbake temperature, postbake time and developer time. Analysis of the data was done using SAS as a software tool.
Development And Evaluation Of Chlorinated Gate Oxides, David H. Fatke
Development And Evaluation Of Chlorinated Gate Oxides, David H. Fatke
Journal of the Microelectronic Engineering Conference
The effect of TCA tube cleaning and oxidation on mobile ion contamination for the growth of gate oxides was Investigated. It was found that the TCA tube clean had a major effect in reduction of mobile ions, while the TCA gate oxide process employed had a negligible effect.
Characterization Of The Perkin-Elmer Model 140 Projection Aligner Exposure Source And Modeling Of Resist Profiles, Arthur Shaun Francomacaro
Characterization Of The Perkin-Elmer Model 140 Projection Aligner Exposure Source And Modeling Of Resist Profiles, Arthur Shaun Francomacaro
Journal of the Microelectronic Engineering Conference
A correlation between scan speed and exposure dose, was obtained for the Perkin-Elmer Model 140 Projection Aligner to Facilitate accurate resist profile modeling. A photovoltaic cell collector with filtering was mounted on a modified wafer chuck to acquire exposure data. The relationship between scan speed and exposure was found to be linear when plotted on log-log scale and predictable to within 57~. Lines of 1.4 urn in Shipley 1400-27 resist and 1.6 urn in KTI 820 resist were successfully imaged. Modeling of the scanner’s output aerial image via PROSIM (Perkin- Elmer resist profile model) was performed with fair results.
Design Of A 4-Bit Pmos Parallel Comparator A/D Converter, Amel Gaddo
Design Of A 4-Bit Pmos Parallel Comparator A/D Converter, Amel Gaddo
Journal of the Microelectronic Engineering Conference
This project dealt with the design of a 4-bit PMOS parallel comparator analog-to-digital converter. Using a predesigned comparator circuit, the rest of the logic was completed. Circuit analysis was performed using SPICE simulation. Circuit layout was done using integrated Circuit Editor (ICE). The PMOS process consists of four masking levels; diffusion, thin oxide, contact cuts, and metal.
Software Analysis Of Capacitance-Voltage Measurements, Richard A. German
Software Analysis Of Capacitance-Voltage Measurements, Richard A. German
Journal of the Microelectronic Engineering Conference
A computer program called CVPLOT, used at RIT to aid in the analysis of metal—oxide—semiconductor (MOS) capacitors, was recoded from REGIS graphics into the VAX Graphical Kernel System (GKS) allowing the user to obtain hardcopy plots of high and low frequency capacitance voltage curves from an HP—Plotter, LNO3 Laser Printer, and LA100 Line Printer. The revised program also allows changes to be made in the values of the ‘non—ideal’ (a nonzero flatband shift) parameters while subsequently observing the shift in the curve as a result of these changes. Curves for three different values of either substrate doping, gate oxide thickness, …
Thickness Measurements Using Prism Coupling, Daniel J. Hahn
Thickness Measurements Using Prism Coupling, Daniel J. Hahn
Journal of the Microelectronic Engineering Conference
A HeNe laser and a 45-90 degree prism with an index of refraction of 1.51 were used to study the prism coupling method of determining the thickness and index of refraction of thin films. This project involved the design and construction of a set-up that allowed for simple adjustment of the incident angle of the light. Based on the available prism, Si02 films were testable.
Advanced Mask Making At Rit, David P. Kanen
Advanced Mask Making At Rit, David P. Kanen
Journal of the Microelectronic Engineering Conference
This project involved the definition of the steps necessary to generate a mask or reticle for any of the three exposure tools (te. GCA lox G-line Stepper, Perkin Elmer Scanning Aligners, and Kasper Contact Aligners) used at RIT. Next a working process for creating chrome masks for the Perkin Elmer Scanners was developed. Using the process outlined in this paper 5 micron line widths can be repeatedly obtained.
Design Of Test Die For Monitoring Manufacturing At Rit, Craig R. Klem
Design Of Test Die For Monitoring Manufacturing At Rit, Craig R. Klem
Journal of the Microelectronic Engineering Conference
This project developed a test chip designed to standardize the testing requirements and characterize bipolar, PMOS and CMOS processes at Rochester Institute of Technology. The comon process monitors were designed to test resistivity, opens and shorts, contact resistance and capacitance. The photolithograPhic monitors were designed to test image resolution and alignment. Process specific discrete devices were designed to test parainetrics and leakage currents. The test chip dies were primarily designed to be inserted onto the mask to eliminate the the need for process monitors on each die and secondly, to periodically monitor the performance of a student run integrated circuit …
An Integrated Approach To Positive Resist Development Characterization, Mozafar Maghsoudnia
An Integrated Approach To Positive Resist Development Characterization, Mozafar Maghsoudnia
Journal of the Microelectronic Engineering Conference
This paper investigates Neureuther and co-workers development model of positive novolak-type photoresist systems in aqueous alkaline developers. A measurement system for determining the exposure and development model parameter! is described. The dissolution rates for two developer solutions have been examined and the impact of the developer differences on resist profiles is illustrated. The dissolution rate of resist in metal ion free developer at various temperatures is investigated.
Time Dependence Of Hot Electron Induced Surface States, Joseph P. Magliocco
Time Dependence Of Hot Electron Induced Surface States, Joseph P. Magliocco
Journal of the Microelectronic Engineering Conference
Hot electron injection was investigated using the HP 4145B SPA to induce Fewler- Nordheim tunneling. High frequency and quasi-static capacitance-voltage (C-V) measurements were taken on p-substrate MOS capacitors in order to generate the distribution of surface states throughout the band gap. The results proved inconclusive with no deformation of the low frequency C-V technique being observed.
Hiac/Royco Particle Counter Installation, Scott H. Mccracken
Hiac/Royco Particle Counter Installation, Scott H. Mccracken
Journal of the Microelectronic Engineering Conference
A HIAC/ROYCO particle monitoring system is being installed to monitor aerosols in the RIT clean room. The system is controlled by a VAX mainframe computer using a Fortran program to read the data from the counter process It and write it to an output file. This file is used to generate control charts monitoring the particle levels at several locations in the cleanroom workspace.
Redesign Of An Eight-Bit, Ecl Dac To Facilitate Speed And Functionality Testing Of A Bi-Cmos Process, William A. Mcgee
Redesign Of An Eight-Bit, Ecl Dac To Facilitate Speed And Functionality Testing Of A Bi-Cmos Process, William A. Mcgee
Journal of the Microelectronic Engineering Conference
The redesign and layout of a clocked eight-bit digital to analog converter using emitter coupled logic is examined based on testing of the original circuit, simulation of ground node resistance and pinout compatibility to a produced part. The completed layout is subjectively compared to the original circuit design. Production and evaluation is pending at this time.
Evaluation Of Plasma Damage To Thin Gate Oxides, Patricia A. Ostling
Evaluation Of Plasma Damage To Thin Gate Oxides, Patricia A. Ostling
Journal of the Microelectronic Engineering Conference
Capacitance-Voltage (C-V) arid Conductance-Voltage (G-V) measurements were performed to characterize field induced charges in thin (300A) oxides subjected to a RF generated oxygen plasma used to remove photoresist. Results based on C-V curves indicate a -4.6V threshold voltage shift for capacitors exposed to the RF plasma as compared to capacitors without plasma processing. Results based on tunnel current measurements were inconclusive.
Wedax Studies On The Hitachi S.E.M., Ronald L. Quiett Jr
Wedax Studies On The Hitachi S.E.M., Ronald L. Quiett Jr
Journal of the Microelectronic Engineering Conference
The WEDAX (Wavelength Dispersive Analysis of X-rays) system incorporated Into the Hitachi S.E.M. is a method of performing chemical microanalysis of a material. The primary objective of this project was to bring up the system to full operating status and calibrate the WEDAX utilizing known samples of aluminum, copper, and silicon. As of May 1988, the S.E.M. resolution Is at 2K and the WEDAX Is still inoperable.