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Accelerating Pattern Recognition Algorithms On Parallel Computing Architectures, Kenneth Rice
Accelerating Pattern Recognition Algorithms On Parallel Computing Architectures, Kenneth Rice
All Dissertations
The move to more parallel computing architectures places more responsibility on the programmer to achieve greater performance. The programmer must now have a greater understanding of the underlying architecture and the inherent algorithmic parallelism. Using parallel computing architectures for exploiting algorithmic parallelism can be a complex task. This dissertation demonstrates various techniques for using parallel computing architectures to exploit algorithmic parallelism. Specifically, three pattern recognition (PR) approaches are examined for acceleration across multiple parallel computing architectures, namely field programmable gate arrays (FPGAs) and general purpose graphical processing units (GPGPUs).
Phase-only filter correlation for fingerprint identification was studied as the first …
Measuring Digital System Latency From Sensing To Actuation At Continuous 1 Millisecond Resolution, Weixin Wu
Measuring Digital System Latency From Sensing To Actuation At Continuous 1 Millisecond Resolution, Weixin Wu
All Theses
This thesis describes a new method for measuring the end-to-end latency between sensing and actuation in a digital computing system. Compared to previous work, which generally measures the latency at 16-33 ms intervals or at discrete events separated by hundreds of ms, our new method measures the latency continuously at 1 millisecond resolution. This allows for the observation of variations in latency over sub 1 s periods, instead of relying upon averages of measurements. We have applied our method to two systems, the ?rst using a camera for sensing and an LCD monitor for actuation, and the second using an …