Engineering Commons^™

Fm Demodulators In Software-Defined Radio Using Fpgas With Rapid Prototyping, Marc Anthony Padilla

Theses and Dissertations

With the advent of software-defined radio, many radio applications have and are currently being designed for FPGAs, due to their high performance and reconfigurability. Invariably, "legacy" waveforms, such as FM, will need to be supported in such systems. A challenge that comes with programming FPGAs is the increased design and implementation time over conventional software programming. In this thesis, three FM demodulator techniques are implemented and compared in an FPGA. Two techniques are found to have similar SNR performance while having very different FPGA implementation characteristics. Library based design is explored for demodulators to increase FPGA design productivity. A block …

Increasing Design Productivity For Fpgas Through Ip Reuse And Meta-Data Encapsulation, Adam T. Arnesen

Theses and Dissertations

As Moore's law continues to progress, it is becoming increasingly difficult for hardware designers to fully utilize the increasing number of transistors available semiconductor devices including FPGAs. This design productivity gap must be addressed to allow designs to take full advantage of the increased logic density that results from rising transistor density. The reuse of previously developed and verified intellectual property (IP) is one approach that has claimed to narrow the design productivity gap. Reuse, however, has proved difficult to realize in practice because of the complexity of IP and the reluctance of designers to reuse IP that they do …

Xdl-Based Hard Macro Generator, Subhrashankha Ghosh

Theses and Dissertations

In a conventional hardware design flow, the compilation process to create the physical circuit on the FPGA takes a long time. HMFlow is a design flow that reduces the compilation time by using pre-compiled modules called hard macros. HMFlow uses System Generator to create the designs, which are then converted to hard macros. The hard macro creation process takes a long time and a possible solution is a hard macro generator called XdlCoreGen, which is described in this thesis. XdlCoreGen can quickly create fully mapped and placed hard macros using XDL. XDL is a human readable design format that describes …

Analysis And Mitigation Of Seu-Induced Noise In Fpga-Based Dsp Systems, Brian Hogan Pratt

Theses and Dissertations

This dissertation studies the effects of radiation-induced single-event upsets (SEUs) on digital signal processing (DSP) systems designed for field-programmable gate arrays (FPGAs). It presents a novel method for evaluating the effects of radiation on DSP and digital communication systems. By using an application-specific measurement of performance in the presence of SEUs, this dissertation demonstrates that only 5-15% of SEUs affecting a communications receiver (i.e. 5-15% of sensitive SEUs) cause critical performance loss. It also reports that the most critical SEUs are those that affect the clock, global reset, and most significant bits (MSBs) of computation. This dissertation also demonstrates …

On-Orbit Fpga Seu Mitigation And Measurement Experiments On The Cibola Flight Experiment Satellite, William A. Howes

Theses and Dissertations

This work presents on-orbit experiments conducted to validate SEU mitigation and detection techniques on FPGA devices and to measure SEU rates in FPGAs and SDRAM. These experiments were designed for the Cibola Flight Experiment Satellite (CFESat), which is an operational technology pathfinder satellite built around 9 Xilinx Virtex FPGAs and developed at Los Alamos National Laboratory. The on-orbit validation experiments described in this work have operated for over four thousand FPGA device days and have validated a variety of SEU mitigation and detection techniques including triple modular redundancy, duplication with compare, reduced precision redundancy, and SDRAM and FPGA block memory …

Development Of A Flexible Fpga-Based Platform For Flight Control System Research, Robert Demott

Theses and Dissertations

This work is part of ongoing research conducted at Virginia Commonwealth University relating to unmanned aerial vehicles. The primary objective of this thesis was to develop a flexible, high-performance autopilot platform in order to facilitate research on advanced flight control algorithms. A dual FPGA-based system architecture utilizing a stacked, multi-board design was created to meet this goal. Processing tasks were split between the two FPGA devices, allowing for improved system timing and increased throughput. A combination of analog and digital filtering techniques were employed in the new system, resulting in enhanced sensor accuracy and precision compared to the previous generation …

Global Positioning System, Vladimir Villalba

Electrical Engineering

The Global Positioning System (GPS) is a navigation network consisting of 24 satellites in orbit around the Earth. This satellite system provides the accurate position of an individual in all weather conditions at all times around the world. Individuals can use GPS receivers to locate where they are, pinpoint where they want to go with any form of transportation.

The senior project embarks in a path to understand the workings of the GPS satellite system. To accomplish this task, the concepts learned in Electrical Engineering will be implemented. This report encompasses the design process and steps taken in prototyping a …

Analysis Of Field Programmable Gate Array-Based Kalman Filter Architectures, Arvind Sudarsanam

All Graduate Theses and Dissertations, Spring 1920 to Summer 2023

A Field Programmable Gate Array (FPGA)-based Polymorphic Faddeev Systolic Array (PolyFSA) architecture is proposed to accelerate an Extended Kalman Filter (EKF) algorithm. A system architecture comprising a software processor as the host processor, a hardware controller, a cache-based memory sub-system, and the proposed PolyFSA as co-processor, is presented. PolyFSA-based system architecture is implemented on a Xilinx Virtex 4 family of FPGAs. Results indicate significant speed-ups for the proposed architecture when compared against a space-based software processor. This dissertation proposes a comprehensive architecture analysis that is comprised of (i) error analysis, (ii) performance analysis, and (iii) area analysis. Results are presented …

An Fpga Based Implementation Of The Exact Stochastic Simulation Algorithm, Phani Bharadwaj Vanguri

Masters Theses

Mathematical and statistical modeling of biological systems is a desired goal for many years. Many biochemical models are often evaluated using a deterministic approach, which uses differential equations to describe the chemical interactions. However, such an approach is inaccurate for small species populations as it neglects the discrete representation of population values, presents the possibility of negative populations, and does not represent the stochastic nature of biochemical systems. The Stochastic Simulation Algorithm (SSA) developed by Gillespie is able to properly account for these inherent noise fluctuations. Due to the stochastic nature of the Monte Carlo simulations, large numbers of simulations …

Design Of An Adaptable Run-Time Reconfigurable Software-Defined Radio Processing Architecture, Joshua R. Templin

All Graduate Theses and Dissertations, Spring 1920 to Summer 2023

Processing power is a key technical challenge holding back the development of a high-performance software defined radio (SDR). Traditionally, SDR has utilized digital signal processors (DSPs), but increasingly complex algorithms, higher data rates, and multi-tasking needs have exceed the processing capabilities of modern DSPs. Reconfigurable computers, such as field-programmable gate arrays (FPGAs), are popular alternatives because of their performance gains over software for streaming data applications like SDR. However, FPGAs have not yet realized the ideal SDR because architectures have not fully utilized their partial reconfiguration (PR) capabilities to bring needed flexibility. A reconfigurable processor architecture is proposed that utilizes …

An Onboard Vision System For Unmanned Aerial Vehicle Guidance, Barrett Bruce Edwards

Theses and Dissertations

The viability of small Unmanned Aerial Vehicles (UAVs) as a stable platform for specific application use has been significantly advanced in recent years. Initial focus of lightweight UAV development was to create a craft capable of stable and controllable flight. This is largely a solved problem. Currently, the field has progressed to the point that unmanned aircraft can be carried in a backpack, launched by hand, weigh only a few pounds and be capable of navigating through unrestricted airspace. The most basic use of a UAV is to visually observe the environment and use that information to influence decision making. …

Acceleration Of Biomolecular Simulations Using Fpga-Based Reconfigurable Computing, Ananth Nallamuthu

All Theses

A paradigm shift is occurring in the way compute-intensive scientific applications are developed. Thanks to advancements in commercially viable hybrid architectures for High-Performance Computing (HPC), the focus has shifted from improving performance by merely scaling algorithms on von Neumann computing nodes to fully exploiting additional computational capabilities provided by accelerators such as FPGAs (Field Programmable Gate Arrays) and GPGPUs (General Purpose Graphical Processing Units).
Computational chemists use Molecular Dynamics (MD) simulations like LAMMPS (Large Scale Atomic Molecular Massively Parallel Systems) and NAMD (NAnoscale Molecular Dynamics) to simulate biomolecular behaviour such as protein folding and small molecule docking to proteins. MD …

Accelerated Frame Data Relocation On Xilinx Field Programmable Gate Array, Ramachandra Kallam

All Graduate Theses and Dissertations, Spring 1920 to Summer 2023

Emerging reconfiguration techniques that include partial dynamic reconfiguration and partial bitstream relocation have been addressed in the past in order to expose the flexibility of field programmable gate array at runtime. Partial bitstream relocation is a technique used to target a partial bitstream of a partial reconfigurable region (PRR) onto other identical reconfigurable regions inside an FPGA, while partial dynamic reconfiguration is used to target a single reconfigurable region. Prior works in this domain aim to minimize "relocation time" with the help of on-chip or on-line processing. In this thesis, a novel PRR-PRR relocation algorithm is proposed and implemented both …

An Efficient Implementation Of An Exponential Random Number Generator In A Field Programmable Gate Array (Fpga), Smitha Gautham

Theses and Dissertations

Many physical, biological, ecological and behavioral events occur at times and rates that are exponentially distributed. Modeling these systems requires simulators that can accurately generate a large quantity of exponentially distributed random numbers, which is a computationally intensive task. To improve the performance of these simulators, one approach is to move portions of the computationally inefficient simulation tasks from software to custom hardware implemented in Field Programmable Gate Arrays (FPGAs). In this work, we study efficient FPGA implementations of exponentially distributed random number generators to improve simulator performance. Our approach is to generate uniformly distributed random numbers using standard techniques …

Synchronization Voter Insertion Algorithms For Fpga Designs Using Triple Modular Redundancy, Jonathan Mark Johnson

Theses and Dissertations

Triple Modular Redundancy (TMR) is a common reliability technique for mitigating single event upsets (SEUs) in FPGA designs operating in radiation environments. For FPGA systems that employ configuration scrubbing, majority voters are needed in all feedback paths to ensure proper synchronization between the TMR replicates. Synchronization voters, however, consume additional resources and impact system timing. This work introduces and contrasts seven algorithms for inserting synchronization voters while automatically performing TMR. The area cost and timing impact of each algorithm on a number of circuit benchmarks is reported. The work demonstrates that one of the algorithms provides the best overall timing …

Reconfigurable Computing For Video Coding, Jian Huang

Electronic Theses and Dissertations

Video coding is widely used in our daily life. Due to its high computational complexity, hardware implementation is usually preferred. In this research, we investigate both ASIC hardware design approach and reconfigurable hardware design approach for video coding applications. First, we present a unified architecture that can perform Discrete Cosine Transform (DCT), Inverse Discrete Cosine Transform (IDCT), DCT domain motion estimation and compensation (DCT-ME/MC). Our proposed architecture is a Wavefront Array-based Processor with a highly modular structure consisting of 8*8 Processing Elements (PEs). By utilizing statistical properties and arithmetic operations, it can be used as a high performance hardware accelerator …

Efficient Implementation Of Raid-6 Encoding And Decoding On A Field Programmable Gate Array (Fpga), David Jacob

Theses and Dissertations

RAID-6 is a data encoding scheme used to provide single drive error detection and dual drive error correction for data redundancy on an array of disks. Here we present a thorough study of efficient implementations of RAID-6 on field programmable gate arrays (FPGAs). Since RAID-6 relies heavily on Galois Field Algebra (GFA), an efficient implementation of a GFA FPGA library is also presented. Through rigorous performance analysis, this work shows the most efficient ways to tradeoff FPGA resources and execution time when implementing GFA functions as well as RAID-6 encoding and decoding.

Memory Architecture Template For Fast Block Matching Algorithms On Field Programmable Gate Arrays, Shant Chandrakar

All Graduate Theses and Dissertations, Spring 1920 to Summer 2023

Fast Block Matching (FBM) algorithms for video compression are well suited for acceleration using parallel data-path architectures on Field Programmable Gate Arrays (FPGAs). However, designing an efficient on-chip memory subsystem to provide the required throughput to this parallel data-path architecture is a complex problem. This thesis presents a memory architecture template that can be parameterized for a given FBM algorithm, number of parallel Processing Elements (PEs), and block size. The template can be parameterized with well known exploration techniques to design efficient on-chip memory subsystems. The memory subsystems are derived for two existing FBM algorithms and are implemented on a …

A Comprehensive Integration And Analysis Of Dynamic Load Balancing Architectures Within Molecular Dynamics, Christopher Reed Rogers

All Graduate Theses and Dissertations, Spring 1920 to Summer 2023

The world of nano-science is an ever-changing field. Molecular Dynamics (MD) is a computational suite of tools that is useful for analyzing and predicting behaviors of substances on the molecular level. The nature of MD is such that only a few types of computations are repeated thousands or sometimes millions of times over. Even a small increase speedup or efficiency of an MD simulator can compound itself over the life of the simulation and have a positive and observable effect. This thesis is the end result of an attempted speedup of the MD problem. Two types of MD architectures are …

Real-Time Optical Flow Sensor Design And Its Application On Obstacle Detection, Zhaoyi Wei

Theses and Dissertations

Motion is one of the most important features describing an image sequence. Motion estimation has been widely applied in structure from motion, vision-based navigation and many other fields. However, real-time motion estimation remains a challenge because of its high computational expense. The traditional CPU-based scheme cannot satisfy the power, size and computation requirements in many applications. With the availability of new parallel architectures such as FPGAs and GPUs, applying these new technologies to computer vision tasks such as motion estimation has been an active research field in recent years. In this dissertation, FPGAs have been applied to real-time motion estimation …

An Optical Flow Implementation Comparison Study, John M. Bodily

Theses and Dissertations

Optical flow is the apparent motion of brightness patterns within an image scene. Algorithms used to calculate the optical flow for a sequence of images are useful in a variety of applications, including motion detection and obstacle avoidance. Typical optical flow algorithms are computationally intense and run slowly when implemented in software, which is problematic since many potential applications of the algorithm require real-time calculation in order to be useful. To increase performance of the calculation, optical flow has recently been implemented on FPGA and GPU platforms. These devices are able to process optical flow in real-time, but are generally …

Real-Time Carrier Frequency Estimation Using Disjoint Pilot Symbol Blocks, Joseph M. Palmer

Theses and Dissertations

Three new and efficient carrier frequency offset estimators are created for the case of disjoint pilot symbol blocks. The estimators are efficient in both a statistical sense and a computational sense. They are formulated to reduce computational cost for use in real-time applications, such as FPGA (field programmable gate array) devices. A reduced cost maximum likelihood (ML) frequency estimator is described. It is a generalization of the approximate ML estimator for a single block of pilot symbols. A number of recent ML estimation techniques are integrated with the purpose of reducing the computational cost while preserving estimation performance. The estimator …

Dynamic Kernel Function For High-Speed Real-Time Fast Fourier Transform Processors, Yu-Heng George Lee

Browse all Theses and Dissertations

The fast Fourier transform (FFT) plays a critical role in many modern applications, such as acoustics, optics, telecommunications, wireless sensor networks, location sensing, patient monitoring, speech, signal detection, and image processing. The input dynamic range, data throughput rate, frequency resolution, bandwidth, design flexibility, hardware consumption, and power requirements for the various applications are vastly different, leading to significant research focusing on different aspects of FFT performance improvement.

The proposed dynamic kernel function uses an efficient fixed-point numerical representation of the twiddle factor and replaces the cumbersome multipliers with simple shift-and-add operations to enhance the data throughput rate for high-speed wideband …

Vector Support For Multicore Processors With Major Emphasis On Configurable Multiprocessors, Hongyan Yang

Dissertations

It recently became increasingly difficult to build higher speed uniprocessor chips because of performance degradation and high power consumption. The quadratically increasing circuit complexity forbade the exploration of more instruction-level parallelism (JLP). To continue raising the performance, processor designers then focused on thread-level parallelism (TLP) to realize a new architecture design paradigm. Multicore processor design is the result of this trend. It has proven quite capable in performance increase and provides new opportunities in power management and system scalability. But current multicore processors do not provide powerful vector architecture support which could yield significant speedups for array operations while maintaining …

Stabilization And Control Of A Quad-Rotor Micro-Uav Using Vision Sensors, Spencer G. Fowers

Theses and Dissertations

Quad-rotor micro-UAVs have become an important tool in the field of indoor UAV research. Indoor flight poses problems not experienced in outdoor applications. The ability to be location- and movement-aware is paramount because of the close proximity of obstacles (walls, doorways, desks). The Helio-copter, an indoor quad-rotor platform that utilizes a compact FPGA board called Helios has been developed in the Robotic Vision Lab at Brigham Young University. Helios allows researchers to perform on-board vision processing and feature tracking without the aid of a ground station or wireless transmission. Using this on-board feature tracking system a drift stabilization control system …

Real-Time Implementation Of Vision Algorithm For Control, Stabilization, And Target Tracking For A Hovering Micro-Uav, Beau J. Tippetts

Theses and Dissertations

A lightweight, powerful, yet efficient quad-rotor platform was designed and constructed to obtain experimental results of completely autonomous control of a hovering micro-UAV using a complete on-board vision system. The on-board vision and control system is composed of a Helios FPGA board, an Autonomous Vehicle Toolkit daughterboard, and a Kestrel Autopilot. The resulting platform is referred to as the Helio-copter. An efficient algorithm to detect, correlate, and track features in a scene and estimate attitude information was implemented with a combination of hardware and software on the FPGA, and real-time performance was obtained. The algorithms implemented include a Harris feature …

Fpga Design Of A Hardware Efficient Pipelined Fft Processor, Ryan T. Bone

Browse all Theses and Dissertations

Digital receivers involve fast Fourier transform (FFT) computations that require a large amount of arithmetic operations. The implementation of a FFT processor is one of the most challenging parts in the realization of a wideband receiver and its hardware complexity is very high. Hence, kernel function FFT processors have been proposed to meet real-time processing requirements and to reduce hardware complexity by rounding the kernel function to predetermined kernel points so as to eliminate the multipliers and use only shifters and adders or subtractors. Because of the nonlinear nature of this approximation by the rounding errors, spurious responses are generated …

High-Speed Data Acquisition And Fpga Detected Pulse Blanking System For Interference Mitigation In Radio Astronomy, Micah Alexander Lillrose

Theses and Dissertations

Radio astronomy is the discipline dedicated to the study of celestial emissions in the radio band from a few MHz to 300 GHz. In recent years, spurious emissions from man-made devices that operate at these frequencies have made detection of astronomical signals difficult. These harmful RF transmissions are called radio frequency interference (RFI). One strategy to remove RFI is to apply spatial filtering using an array antenna. This thesis documents the development of a high-speed data acquisition system used to record data from 7- and 19-element phased array feeds. The system supports synchronous sampling over all channels and streams data …

Hardware Support For A Configurable Architecture For Real-Time Embedded Systems On A Programmable Chip, Spencer W. Isaacson

Theses and Dissertations

Current FPGA technology has advanced to the point that useful embedded SoPCs can now be designed. The Real Time Processor (RTP) project at Brigham Young University leverages the advances in FPGA technology with a system architecture that is customizable to specific applications. A simple real-time processor has been designed to provide support for a hardware-assisted real-time operating system providing fast context switches. As part of the hardware RTOS, the following have been implemented in hardware: scheduler, register banks, mutex, semaphore, queue, interrupts, event, and others. A novel circuit called the Task-Resource Matrix has been created to allow fast inter/intra processor …

Compilation And Generation Of Multi-Processor On A Chip Real-Time Embedded Systems, Randall S. Klingler

Theses and Dissertations

Current FPGA technology has advanced to the point that useful embedded System-on-Programmable-Chips (SoPC)s can now be designed. The Real Time Processor (RTP) project leverages the advances in FPGA technology with a system architecture that is customizable to specific real-time applications. The design and implementation of the framework for architecting such a system from ANSI-C code is presented. The Small Device C Compiler (SDCC) was retargeted to the RTP architecture and extended to produce a generator directive file. The RTPGen hardware generator was created to consume the directive file and produce a highly customized top-level structural VHDL file that can be …