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Full-Text Articles in Engineering
Accelerating Pattern Recognition Algorithms On Parallel Computing Architectures, Kenneth Rice
Accelerating Pattern Recognition Algorithms On Parallel Computing Architectures, Kenneth Rice
All Dissertations
The move to more parallel computing architectures places more responsibility on the programmer to achieve greater performance. The programmer must now have a greater understanding of the underlying architecture and the inherent algorithmic parallelism. Using parallel computing architectures for exploiting algorithmic parallelism can be a complex task. This dissertation demonstrates various techniques for using parallel computing architectures to exploit algorithmic parallelism. Specifically, three pattern recognition (PR) approaches are examined for acceleration across multiple parallel computing architectures, namely field programmable gate arrays (FPGAs) and general purpose graphical processing units (GPGPUs).
Phase-only filter correlation for fingerprint identification was studied as the first …
Improved Stereo Vision Methods For Fpga-Based Computing Platforms, Wade S. Fife
Improved Stereo Vision Methods For Fpga-Based Computing Platforms, Wade S. Fife
Theses and Dissertations
Stereo vision is a very useful, yet challenging technology for a wide variety of applications. One of the greatest challenges is meeting the computational demands of stereo vision applications that require real-time performance. The FPGA (Field Programmable Gate Array) is a readily-available technology that allows many stereo vision methods to be implemented while meeting the strict real-time performance requirements of some applications. Some of the best results have been obtained using non-parametric stereo correlation methods, such as the rank and census transform. Yet relatively little work has been done to study these methods or to propose new algorithms based on …
Fpga Bootstrapping Using Partial Reconfiguration, Patrick Sutton Ostler
Fpga Bootstrapping Using Partial Reconfiguration, Patrick Sutton Ostler
Theses and Dissertations
Partial reconfiguration (PR) is the process of configuring a subset of resources on a Field Programmable Gate Array (FPGA) while the remainder of the device continues to operate. PR extends the usability of FPGAs and makes it possible to perform design bootstrapping. Just like bootstrapping in PCs, bootstrapping in FPGAs consists of using a small application to initialize basic services and load a larger, more complex application to the device. Bootstrapping allows for unique design applications that can be used to maintain communication services, increase design security, reduce initial configuration time, and reduce nonvolatile configuration memory storage. This thesis presents …
Turbo Bayesian Compressed Sensing, Depeng Yang
Turbo Bayesian Compressed Sensing, Depeng Yang
Doctoral Dissertations
Compressed sensing (CS) theory specifies a new signal acquisition approach, potentially allowing the acquisition of signals at a much lower data rate than the Nyquist sampling rate. In CS, the signal is not directly acquired but reconstructed from a few measurements. One of the key problems in CS is how to recover the original signal from measurements in the presence of noise. This dissertation addresses signal reconstruction problems in CS. First, a feedback structure and signal recovery algorithm, orthogonal pruning pursuit (OPP), is proposed to exploit the prior knowledge to reconstruct the signal in the noise-free situation. To handle the …
Automated Fixed-Point Analysis And Bit Width Selection In Digital Signal Processing Circuits Using Ptolemy, Derrick S. Gibelyou
Automated Fixed-Point Analysis And Bit Width Selection In Digital Signal Processing Circuits Using Ptolemy, Derrick S. Gibelyou
Theses and Dissertations
When designing custom hardware to implement signal processing algorithms, it is important to select bitwidths that meet the minimum error requirements while minimizing implementation area. Larger bitwidths reduce error, but increase area, while selecting smaller bitwidths does the opposite. Finding the set of bitwidths that produces the smallest area that still meets the error requirements has been shown to be NP-hard. To address this problem, many heuristics have been developed. Unfortunately, they are not always well documented and do not have available source code. It is also di cult to know which algorithm to try to use. This thesis addresses …
Development Of An Experimental Phased-Array Feed System And Algorithms For Radio Astronomy, Jonathan Charles Landon
Development Of An Experimental Phased-Array Feed System And Algorithms For Radio Astronomy, Jonathan Charles Landon
Theses and Dissertations
Phased array feeds (PAFs) are a promising new technology for astronomical radio telescopes. While PAFs have been used in other fields, the demanding sensitivity and calibration requirements in astronomy present unique new challenges. This dissertation presents some of the first astronomical PAF results demonstrating the lowest noise temperature and highest sensitivity at the time (66 Kelvin and 3.3 m^2/K, respectively), obtained using a narrowband (425 kHz bandwidth) prototype array of 19 linear co-polarized L-band dipoles mounted at the focus of the Green Bank 20 Meter Telescope at the National Radio Astronomy Observatory (NRAO) in Green Bank, West Virginia. Results include …
Fpga Communication Framework For Communication, Debugging, Testing, And Rapid Prototyping, Peter Andrew Lieber
Fpga Communication Framework For Communication, Debugging, Testing, And Rapid Prototyping, Peter Andrew Lieber
Theses and Dissertations
FPGA-CF is an open-source, portable, extensible communications framework that consists of a small hardware core (less than 600 slices) and a software library/API (Java and C++). It enables a host PC to transmit data at 120 Mb/s to Xilinx-based FPGA boards via Ethernet using standard inter-networking protocols (UDP/IP). A custom lightweight connection-oriented protocol guarantees reliability. The hardware core is directly connected to the Xilinx internal configuration port (ICAP) and supports all ICAP functionality. The core also provides an extensible user-channel interface and provides up to 15, 8-bit user-data channels that can be connected to user circuitry (configurable by the user). …
Towards Securing Virtualization Using A Reconfigurable Platform, Tushar Janefalkar
Towards Securing Virtualization Using A Reconfigurable Platform, Tushar Janefalkar
All Theses
Virtualization is no longer limited to main stream processors and servers. Virtualization software for General Purpose Processors (GPP) that allow one Operating System (OS) to run as an application in another OS have become commonplace. To exploit the full potential of the available hardware, virtualization is now prevalent across all systems big and small. Besides GPPs, state-of-the-art embedded processors are now capable of running rich operating systems and their virtualization is now a hot topic of research. However, this technological progress also opens doors for attackers to snoop on data that is not only confined to storage servers but also …
Field-Programmable Gate Array Implementation Of A Scalable Integral Image Architecture Based On Systolic Arrays, Juan Alberto De La Cruz
Field-Programmable Gate Array Implementation Of A Scalable Integral Image Architecture Based On Systolic Arrays, Juan Alberto De La Cruz
All Graduate Theses and Dissertations, Spring 1920 to Summer 2023
The integral image representation of an image is important for a large number of modern image processing algorithms. Integral image representations can reduce computation and increase the operating speed of certain algorithms, improving real-time performance. Due to increasing demand for real-time image processing performance, an integral image architecture capable of accelerating the calculation based on the amount of available resources is presented. Use of the proposed accelerator allows for subsequent stages of a design to have data sooner and execute in parallel. It is shown here how, with some additional resources used in the Field Programmable Gate Array (FPGA), a …
Fm Demodulators In Software-Defined Radio Using Fpgas With Rapid Prototyping, Marc Anthony Padilla
Fm Demodulators In Software-Defined Radio Using Fpgas With Rapid Prototyping, Marc Anthony Padilla
Theses and Dissertations
With the advent of software-defined radio, many radio applications have and are currently being designed for FPGAs, due to their high performance and reconfigurability. Invariably, "legacy" waveforms, such as FM, will need to be supported in such systems. A challenge that comes with programming FPGAs is the increased design and implementation time over conventional software programming. In this thesis, three FM demodulator techniques are implemented and compared in an FPGA. Two techniques are found to have similar SNR performance while having very different FPGA implementation characteristics. Library based design is explored for demodulators to increase FPGA design productivity. A block …
Increasing Design Productivity For Fpgas Through Ip Reuse And Meta-Data Encapsulation, Adam T. Arnesen
Increasing Design Productivity For Fpgas Through Ip Reuse And Meta-Data Encapsulation, Adam T. Arnesen
Theses and Dissertations
As Moore's law continues to progress, it is becoming increasingly difficult for hardware designers to fully utilize the increasing number of transistors available semiconductor devices including FPGAs. This design productivity gap must be addressed to allow designs to take full advantage of the increased logic density that results from rising transistor density. The reuse of previously developed and verified intellectual property (IP) is one approach that has claimed to narrow the design productivity gap. Reuse, however, has proved difficult to realize in practice because of the complexity of IP and the reluctance of designers to reuse IP that they do …
Xdl-Based Hard Macro Generator, Subhrashankha Ghosh
Xdl-Based Hard Macro Generator, Subhrashankha Ghosh
Theses and Dissertations
In a conventional hardware design flow, the compilation process to create the physical circuit on the FPGA takes a long time. HMFlow is a design flow that reduces the compilation time by using pre-compiled modules called hard macros. HMFlow uses System Generator to create the designs, which are then converted to hard macros. The hard macro creation process takes a long time and a possible solution is a hard macro generator called XdlCoreGen, which is described in this thesis. XdlCoreGen can quickly create fully mapped and placed hard macros using XDL. XDL is a human readable design format that describes …
Analysis And Mitigation Of Seu-Induced Noise In Fpga-Based Dsp Systems, Brian Hogan Pratt
Analysis And Mitigation Of Seu-Induced Noise In Fpga-Based Dsp Systems, Brian Hogan Pratt
Theses and Dissertations
This dissertation studies the effects of radiation-induced single-event upsets (SEUs) on digital signal processing (DSP) systems designed for field-programmable gate arrays (FPGAs). It presents a novel method for evaluating the effects of radiation on DSP and digital communication systems. By using an application-specific measurement of performance in the presence of SEUs, this dissertation demonstrates that only 5-15% of SEUs affecting a communications receiver (i.e. 5-15% of sensitive SEUs) cause critical performance loss. It also reports that the most critical SEUs are those that affect the clock, global reset, and most significant bits (MSBs) of computation. This dissertation also demonstrates …
On-Orbit Fpga Seu Mitigation And Measurement Experiments On The Cibola Flight Experiment Satellite, William A. Howes
On-Orbit Fpga Seu Mitigation And Measurement Experiments On The Cibola Flight Experiment Satellite, William A. Howes
Theses and Dissertations
This work presents on-orbit experiments conducted to validate SEU mitigation and detection techniques on FPGA devices and to measure SEU rates in FPGAs and SDRAM. These experiments were designed for the Cibola Flight Experiment Satellite (CFESat), which is an operational technology pathfinder satellite built around 9 Xilinx Virtex FPGAs and developed at Los Alamos National Laboratory. The on-orbit validation experiments described in this work have operated for over four thousand FPGA device days and have validated a variety of SEU mitigation and detection techniques including triple modular redundancy, duplication with compare, reduced precision redundancy, and SDRAM and FPGA block memory …