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Full-Text Articles in Engineering
Investigation Of Solution Space Of Trees And Dags For Realization Of Combinational Logic In At 6000 Series Fpgas, Philip Ho
Dissertations and Theses
Various tree and Directed Acyclic Graph structures have been used for representation and manipulation of switching functions. Among these structures the Binary Decision DiagramJilave been the most widely used in logic synthesis. A BDD is a binary tree graph that represents the recursive execution of Shannon's expansion. A FDD is a directed function graph that represents the recursive execution of Reed Muller expansion. A family of decision diagrams for representation of Boolean function is introduced in this thesis. This family of Kronecker Functional Decision Diagrams (KFDD) includes the Binary Decision Diagrams (BDD) and Functional Decision Diagrams (FDD) as subsets. Due …
Vertex Ordering For A Partitioning-Based Fitting Algorithm For An Epld Device, Tongjun Gao
Vertex Ordering For A Partitioning-Based Fitting Algorithm For An Epld Device, Tongjun Gao
Dissertations and Theses
As the Application-Specific Integrated Circuit(ASIC) technology develops to the trend of high density and modulization, the ASIC device market has been dominated gradually by the more complex Erasable Programmable Logic Devices (EPLDs) and the Field Programmable Gate Array(FPGAs) instead of the ordinally Programmable Logic Devices(PLDs). Meanwhile, the design automation system for such programmable devices has also moved from schematic entry design to high level hardware description language entry design. Usually, the whole design automation process consists of three phrases, the high level hardware description language compiler, the logic synthesis stage and the layout synthesis stage. Though the layout synthesis stage …
Designing And Simulating A Multistage Sampling Rate Conversion System Using A Set Of Pc Programs, David Joseph Hagerty
Designing And Simulating A Multistage Sampling Rate Conversion System Using A Set Of Pc Programs, David Joseph Hagerty
Dissertations and Theses
The thesis covers a series of PC programs that we have written that will enable users to easily design FIR linear phase lowpass digital filters and multistage sampling rate conversion systems. The first program is a rewrite of the McClellan-Parks computer program with some slight modifications. The second program uses an algorithm proposed by Rabiner that determines the length of a lowpass digital filter. Rabiner used a formula proposed by Herrmann et al. to initially estimate the filter length in his algorithm. The formula, however, assumes unity gain. We present a modification to the formula so that the gain of …
Quasi-Static Deflection Compensation Control Of Flexible Manipulator, Jingbin Feng
Quasi-Static Deflection Compensation Control Of Flexible Manipulator, Jingbin Feng
Dissertations and Theses
The growing need in industrial applications of high-performance robots has led to designs of lightweight robot arms. However the light-weight robot arm introduces accuracy and vibration problems. The classical robot design and control method based on the rigid body assumption is no longer satisfactory for the light-weight manipulators. The effects of flexibility of light-weight manipulators have been an active research area in recent years. A new approach to correct the quasi-static position and orientation error of the end-effector of a manipulator with flexible links is studied in this project. In this approach, strain gages are used to monitor the elastic …
A Robust High Precision Algorithm For Sinewave Parameter Estimation, Kendall Ann Rydell
A Robust High Precision Algorithm For Sinewave Parameter Estimation, Kendall Ann Rydell
Dissertations and Theses
The estimation of sinewave parameters has many practical applications in test and data processing systems. Measuring the effective bits of an analog-to-digital converter and linear circuit identification are some typical examples. If a sinew ave's frequency is known, there is an established linear method to estimate the other parameters. But when none of the parameters are known (which is usually the case in practical situations), the estimation problem becomes more difficult. Traditional approaches to this task applied an iterative, sinewave curve-fit algorithm. Two problems with this technique are that convergence is often slow and not always guaranteed and the results …
Minimization Of Permuted Reed-Muller Trees And Reed-Muller Trees For Cellular Logic Programmable Gate Arrays, Lifei Wu
Dissertations and Theses
The new family of Field Programmable Gate Arrays, CLI 6000 from Concurrent Logic Inc realizes truly Cellular Logic. It has been mainly designed for the realization of data path architectures. However, the realizable logic functions provided by its macrocells and their limited connectivity call also for new general-purpose logic synthesis methods. The basic cell of CLi 6000 can be programmed to realize a two-input multiplexer ( A*B + C*B ), an AND/EXOR cell ( A*B Ea C ), or the basic 2-input AND, OR and EXOR gate. This suggests to using these cells for tree-like expansions. These "cellular logic" devices …