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## Full-Text Articles in Engineering

Tetrahedral Mesh Optimization And Generation Via Topological Transformations And Gradient Based Node Perturbation, Christopher B. Hilbert

#### Tetrahedral Mesh Optimization And Generation Via Topological Transformations And Gradient Based Node Perturbation, Christopher B. Hilbert

*Masters Theses and Doctoral Dissertations*

A general tetrahedral mesh optimization scheme utilizing both topological changes (i.e. flips) and gradient-based vertex optimization (i.e. smoothing) is demonstrated. This scheme is used in the optimization of tetrahedral meshes created by third-party software as well as a grid generation methodology created for this work. The particular algorithms involved are explained in detail including, an explication of the primary optimization metric, weighted condition number. In addition, a thorough literature review regarding tetrahedral mesh generation is given.

Compressive Sensing Based Imaging Via Belief Propagation, Preethi Modur Ramachandra

#### Compressive Sensing Based Imaging Via Belief Propagation, Preethi Modur Ramachandra

*Masters Theses and Doctoral Dissertations*

Multiple description coding (MDC) using Compressive Sensing (CS) mainly aims at restoring an image from a small subset of samples with reasonable accuracy using an iterative message passing decoding algorithm commonly known as Belief Propagation (BP). The CS technique can accurately recover any compressible or sparse signal from a lesser number of non-adaptive, randomized linear projection samples than that specified by the Nyquist rate. In this work, we demonstrate how CS-based encoding generates measurements from the sparse image signal and the measurement matrix. Then we demonstrate how a BP decoding algorithm reconstructs the image from the measurements generated. In our ...

Fully Anisotropic Split-Tree Adaptive Refinement Mesh Generation Using Tetrahedral Mesh Stitching, Vincent Charles Betro

#### Fully Anisotropic Split-Tree Adaptive Refinement Mesh Generation Using Tetrahedral Mesh Stitching, Vincent Charles Betro

*Masters Theses and Doctoral Dissertations*

Due to the myriad of geometric topologies that modern computational fluid dynamicists desire to mesh and run solutions on, the need for a robust Cartesian Mesh Generation algorithm is paramount. Not only do Cartesian meshes require less elements and often help resolve flow features but they also allow the grid generator to have a great deal of control in so far as element aspect ratio, size, and gradation. Fully Anisotropic Split-Tree Adaptive Refinement (FASTAR) is a code that allows the user to exert a great deal of control and ultimately generate a valid, geometry conforming mesh. Due to the split-tree ...

Waypoint Generation Based On Sensor Aimpoint, Shannon M. Farrell

#### Waypoint Generation Based On Sensor Aimpoint, Shannon M. Farrell

*Theses and Dissertations*

Secretary of Defense Robert M. Gates has emphasized a need for a greater number of intelligence, surveillance, and reconnaissance (ISR) assets to support combatant commanders and military operations globally. Unmanned systems, especially MAVs, used as ISR platforms provide the ability to maintain covertness during missions and help reduce the risk to human life. This research develops waypoint generation algorithms required to keep a point of interest (POI) in the field of view (FOV) of a fixed sensor on a micro air vehicle (MAV) in the presence of a constant wind.

Fixed sensors, while cheaper and less prone to mechanical failure ...

Use Of Tabu Search In A Solver To Map Complex Networks Onto Emulab Testbeds, Jason E. Macdonald

#### Use Of Tabu Search In A Solver To Map Complex Networks Onto Emulab Testbeds, Jason E. Macdonald

*Theses and Dissertations*

The University of Utah's solver for the testbed mapping problem uses a simulated annealing metaheuristic algorithm to map a researcher's experimental network topology onto available testbed resources. This research uses tabu search to find near-optimal physical topology solutions to user experiments consisting of scale-free complex networks. While simulated annealing arrives at solutions almost exclusively by chance, tabu search incorporates the use of memory and other techniques to guide the search towards good solutions. Both search algorithms are compared to determine whether tabu search can produce equal or higher quality solutions than simulated annealing in a shorter amount of ...

Improved Hyperspectral Image Testing Using Synthetic Imagery And Factorial Designed Experiments, Joseph P. Bellucci

#### Improved Hyperspectral Image Testing Using Synthetic Imagery And Factorial Designed Experiments, Joseph P. Bellucci

*Theses and Dissertations*

The goal of any remote sensing system is to gather data about the geography it is imaging. In order to gain knowledge of the earth's landscape, post-processing algorithms are developed to extract information from the collected data. The algorithms can be intended to classify the various ground covers in a scene, identify specific targets of interest, or detect anomalies in an image. After the design of an algorithm comes the difficult task of testing and evaluating its performance. Traditionally, algorithms are tested using sets of extensively ground truthed test images. However, the lack of well characterized test data sets ...

Ternary Quantum Logic, Normen Giesecke

#### Ternary Quantum Logic, Normen Giesecke

*Dissertations and Theses*

The application of Moore's Law would not be feasible by using the computing systems fabrication principles that are prevalent today. Fundamental changes in the field of computing are needed to keep Moore's Law operational. Different quantum technologies are available to take the advancement of computing into the future. Logic in quantum technology uses gates that are very different from those used in contemporary technology. Limiting itself to reversible operations, this thesis presents different methods to realize these logic gates. Two methods using Generalized Ternary Gates and Muthukrishnan Stroud Gates are presented for synthesis of ternary logic gates. Realizations ...

Image Quality Assessment Using Artificial Neural Networks, Alexander Havstad

#### Image Quality Assessment Using Artificial Neural Networks, Alexander Havstad

*Theses: Doctorates and Masters*

not available

Development Of Self-Adaptive Back Propagation And Derivative Free Training Algorithms In Artificial Neural Networks, Shamsuddin Ahmed

#### Development Of Self-Adaptive Back Propagation And Derivative Free Training Algorithms In Artificial Neural Networks, Shamsuddin Ahmed

*Theses: Doctorates and Masters*

Three new iterative, dynamically self-adaptive, derivative-free and training parameter free artificial neural network (ANN) training algorithms are developed. They are defined as self-adaptive back propagation, multi-directional and restart ANN training algorithms. The descent direction in self-adaptive back propagation training is determined implicitly by a central difference approximation scheme, which chooses its step size according to the convergence behavior of the error function. This approach trains an ANN when the gradient information of the corresponding error function is not readily available. The self- adaptive variable learning rates per epoch are determined dynamically using a constrained interpolation search. As a result, appropriate ...

Improving The Run Time Of The Decomposition Algorithm For Fault Tolerant Clos Interconnection Networks Through Swap Re-Ordering, Andrea Laura Mcmakin

#### Improving The Run Time Of The Decomposition Algorithm For Fault Tolerant Clos Interconnection Networks Through Swap Re-Ordering, Andrea Laura Mcmakin

*Theses*

Clos interconnection networks, used in data networks and computing systems, can contain extra switches to be used in faulty conditions. The speed of such fault tolerant Clos interconnection networks is improved through the use these switches in no-fault situations. The network can be represented by a matrix, which is then decomposed using an algorithm, and the switch settings are thus assigned.

The original decomposition algorithm consisted of four element swaps in the following order: wild swap, simple swap, next simple swap, and successive swap. However, by re-arranging these swaps with the simple swap first, followed by the next simple and ...

Jitter And Wander Reduction For A Sonet Ds3 Desynchronizer Using Predictive Fuzzy Control, Kevin Blythe Stanton

#### Jitter And Wander Reduction For A Sonet Ds3 Desynchronizer Using Predictive Fuzzy Control, Kevin Blythe Stanton

*Dissertations and Theses*

Excessive high-frequency jitter or low-frequency wander can create problems within synchronous transmission systems and must be kept within limits to ensure reliable network operation. The emerging Synchronous Optical NETwork (SONET) introduces additional challenges for jitter and wander attenuation equipment (called desynchronizers) when used to carry payloads from the existing Plesiochronous Digital Hierarchy (PDH), such as the DS3. The difficulty is primarily due to the large phase transients resulting from the pointer-based justification technique employed by SONET (called Pointer Justification Events or PJEs). While some previous desynchronization techniques consider the buffer level in their control actions, none has explicitly considered wander ...

Minimization Of Sum-Of-Conditional-Decoders Structures With Applications In Finite Machine Epld Design And Machine Learning, Sanof Mohamedsadakathulla

#### Minimization Of Sum-Of-Conditional-Decoders Structures With Applications In Finite Machine Epld Design And Machine Learning, Sanof Mohamedsadakathulla

*Dissertations and Theses*

In order to achieve superior speed in sequencer designs over competing PLD devices, Cypress brought to market an innovative architecture, CY7C361. This architecture introduced a new kind of universal logic gate, the CONDITION DECODER (CDEC). Because there are only 32 macrocells in the chip, saving only one CDEC gate can be quite important (the well-known "fit/no-fit problem"). A problem that is related to the fitting problem of the Cypress CY7C361 chip is the SOC Minimization. Due to the limited low number of macrocells in CY7C361, a high quality logic minimization to reduce the number of macrocells is very important ...

An Analysis Of Approaches To Efficient Hardware Realization Of Image Compression Algorithms, Kamran Iravani

#### An Analysis Of Approaches To Efficient Hardware Realization Of Image Compression Algorithms, Kamran Iravani

*Dissertations and Theses*

In this thesis an attempt has been made to develop a fast algorithm to compress images. The Reed-Muller compression algorithm which was introduced by Reddy & Pai [3] is fast, but the compression factor is too low when compared to the other methods. In this thesis first research has been done to improve this method by generalizing the Reed-Muller transform to the fixed polarity Reed-Muller form. This thesis shows that the Fixed Polarity Reed-Muller transform does not improve the compression factor enough to warrant its use as an image compression method. The paper, by Reddy & Pai [3], on Reed-Muller image compression ...

High Level Preprocessor Of A Vhdl-Based Design System, Karthikeyan Palanisamy

#### High Level Preprocessor Of A Vhdl-Based Design System, Karthikeyan Palanisamy

*Dissertations and Theses*

This thesis presents the work done on a design automation system in which high-level synthesis is integrated with logic synthesis. DIADESfa design automation system developed at PSU, starts the synthesis process from a language called ADL. The major part of this thesis deals with transforming the ADL -based DIADES system into a VHDL -based DIADES system. In this thesis I have upgraded and modified the existing DIADES system so that it becomes a preprocessor to a comprehensive VHDL -based design system from Mentor Graphics. The high-level synthesis in the DIADES system includes two stages: data path synthesis and control unit ...

Minimization Of Generalized Reed-Muller Expansion And Its Sub-Class, Xiaoqiang Zeng

#### Minimization Of Generalized Reed-Muller Expansion And Its Sub-Class, Xiaoqiang Zeng

*Dissertations and Theses*

Several classes of AND-EXOR circuit expressions have been defined and their relationship have been shown. A new class of AND-EXOR circuit, the Partially Mixed Polarity Reed-Muller Expression(PMPRM), which is a subclass of the Generalized Reed-Muller expression, is created, along with an efficient minimization algorithm. This new AND/EXOR circuit form has the following features: • Since this sub-family of ESOP (with a total of n2n-I22n-i - (n-1)2n forms which includes the 2n Fixed-Polarity Reed-Muller forms) is much larger than the Kronecker Reed-Muller(KRM) expansion(with 3n forms), generally the minimal form of this expansion will be much closer to the ...

#### Investigation Of Solution Space Of Trees And Dags For Realization Of Combinational Logic In At 6000 Series Fpgas, Philip Ho

*Dissertations and Theses*

Various tree and Directed Acyclic Graph structures have been used for representation and manipulation of switching functions. Among these structures the Binary Decision DiagramJilave been the most widely used in logic synthesis. A BDD is a binary tree graph that represents the recursive execution of Shannon's expansion. A FDD is a directed function graph that represents the recursive execution of Reed Muller expansion. A family of decision diagrams for representation of Boolean function is introduced in this thesis. This family of Kronecker Functional Decision Diagrams (KFDD) includes the Binary Decision Diagrams (BDD) and Functional Decision Diagrams (FDD) as subsets ...

Vertex Ordering For A Partitioning-Based Fitting Algorithm For An Epld Device, Tongjun Gao

#### Vertex Ordering For A Partitioning-Based Fitting Algorithm For An Epld Device, Tongjun Gao

*Dissertations and Theses*

As the Application-Specific Integrated Circuit(ASIC) technology develops to the trend of high density and modulization, the ASIC device market has been dominated gradually by the more complex Erasable Programmable Logic Devices (EPLDs) and the Field Programmable Gate Array(FPGAs) instead of the ordinally Programmable Logic Devices(PLDs). Meanwhile, the design automation system for such programmable devices has also moved from schematic entry design to high level hardware description language entry design. Usually, the whole design automation process consists of three phrases, the high level hardware description language compiler, the logic synthesis stage and the layout synthesis stage. Though the ...

Quasi-Static Deflection Compensation Control Of Flexible Manipulator, Jingbin Feng

#### Quasi-Static Deflection Compensation Control Of Flexible Manipulator, Jingbin Feng

*Dissertations and Theses*

The growing need in industrial applications of high-performance robots has led to designs of lightweight robot arms. However the light-weight robot arm introduces accuracy and vibration problems. The classical robot design and control method based on the rigid body assumption is no longer satisfactory for the light-weight manipulators. The effects of flexibility of light-weight manipulators have been an active research area in recent years. A new approach to correct the quasi-static position and orientation error of the end-effector of a manipulator with flexible links is studied in this project. In this approach, strain gages are used to monitor the elastic ...

A Robust High Precision Algorithm For Sinewave Parameter Estimation, Kendall Ann Rydell

#### A Robust High Precision Algorithm For Sinewave Parameter Estimation, Kendall Ann Rydell

*Dissertations and Theses*

The estimation of sinewave parameters has many practical applications in test and data processing systems. Measuring the effective bits of an analog-to-digital converter and linear circuit identification are some typical examples. If a sinew ave's frequency is known, there is an established linear method to estimate the other parameters. But when none of the parameters are known (which is usually the case in practical situations), the estimation problem becomes more difficult. Traditional approaches to this task applied an iterative, sinewave curve-fit algorithm. Two problems with this technique are that convergence is often slow and not always guaranteed and the ...

#### Minimization Of Permuted Reed-Muller Trees And Reed-Muller Trees For Cellular Logic Programmable Gate Arrays, Lifei Wu

*Dissertations and Theses*

The new family of Field Programmable Gate Arrays, CLI 6000 from Concurrent Logic Inc realizes truly Cellular Logic. It has been mainly designed for the realization of data path architectures. However, the realizable logic functions provided by its macrocells and their limited connectivity call also for new general-purpose logic synthesis methods. The basic cell of CLi 6000 can be programmed to realize a two-input multiplexer ( A*B + C*B ), an AND/EXOR cell ( A*B Ea C ), or the basic 2-input AND, OR and EXOR gate. This suggests to using these cells for tree-like expansions. These "cellular logic" devices require ...

#### Minimization Of Exclusive Sum Of Products Expressions For Multiple-Valued Input Incompletely Specified Functions, Ning Song

*Dissertations and Theses*

In recent years, there is an increased interest in the design of logic circuits which use EXOR gates. Particular interest is in the minimization of arbitrary Exclusive Sums Of Products (ESOPs). Functions realized by such circuits can have fewer gates, fewer connections, and take up less area in VLSI and especially, FPGA realizations. They are also easily testable. So far, the ESOPs are not as popular as their Sum of Products (SOP) counterparts. One of the main reasons it that the problem of the minimization of ESOP circuits was traditionally an extremely difficult one. Since exact solutions can be practically ...

Mapping Programs To Parallel Architectures In The Real World, Dezheng Tang

#### Mapping Programs To Parallel Architectures In The Real World, Dezheng Tang

*Dissertations and Theses*

Mapping an application program to a parallel architecture can be described as a multidimensional optimization problem. To simplify the problem, we divide the overall mapping process into three sequential substeps: partitioning, allocating, and scheduling, with each step using a few details of the program and architecture description. Due to the difficulty in accurately describing the program and architecture and the fact that each substep uses incomplete information, inaccuracy is pervasive in the real-world mapping process. We hypothesize that the inaccuracy and the use of suboptimal, heuristic mapping methods may greatly affect the mapping or submapping performance and lead to a ...

A Partitioning-Based Approach To The Fitting Problem In Special Architecture Eplds, Steffan Goller

#### A Partitioning-Based Approach To The Fitting Problem In Special Architecture Eplds, Steffan Goller

*Dissertations and Theses*

In this thesis, we describe an architecture-driven fitting algorithm for an Application-Specific EPLD, the CY7C361, from Cypress Semiconductor. Traditional placement and routing tools for PLDs perform placement and routing separately. Several placement possibilities are created and the router tries to realize the connections between the physical locations of the cells on the chip. The Cypress CY7C361 has a very unique chip architecture with a highly limited connectivity between the physical cells. Therefore, it is necessary to consider the mutability when the placement of cells is performed. The combination of the two stages is called fitting. The specific architecture-dependent constraints, imposed ...

Effectiveness Of Additive Correction Multigrid In Numerical Heat Transfer Analysis When Implemented On An Intel Ipsc2, James D. Padgett

#### Effectiveness Of Additive Correction Multigrid In Numerical Heat Transfer Analysis When Implemented On An Intel Ipsc2, James D. Padgett

*Dissertations and Theses*

The effectiveness of the Additive Correction Multigrid (ACM) algorithm, a line-byline Tri-diagonal Matrix Algorithm (TDMA), and simple Gauss-Seidel (GS) iteration in numerical heat transfer analysis is investigated on a conventional single processor computer and on a distributed memory parallel computer. The performance of these methods is studied by solving a two-dimensional, steady heat conduction problem. The execution time of ACM on a single processor is proportional to the number of unknowns to the 1.5 power. This is in contrast to the execution time of the TDMA for which the execution time is proportional to the number of unknowns to ...

Ignoring Interprocessor Communication During Scheduling, Chintamani M. Patwardhan

#### Ignoring Interprocessor Communication During Scheduling, Chintamani M. Patwardhan

*Dissertations and Theses*

The goal of parallel processing is to achieve high speed computing by partitioning a program into concurrent parts, assigning them in an efficient way to the available processors, scheduling the program and then executing the concurrent parts simultaneously. In the past researchers have combined the allocation of tasks in a program and scheduling of those tasks into one operation. We define scheduling as a process of efficiently assigning priorities to the already allocated tasks in a program. Assignment of priorities is important in cases when more than one task at a processor is ready for execution. Most heuristics for scheduling ...

Improved I/O Pad Positions Assignment Algorithm For Sea-Of-Gates Placement, Shyang-Kuen Her

#### Improved I/O Pad Positions Assignment Algorithm For Sea-Of-Gates Placement, Shyang-Kuen Her

*Dissertations and Theses*

A new heuristic method to improve the I/O pad assignment for the sea-of-gates placement algorithm "PROUD" is proposed. In PROUD, the preplaced I/O pads are used as the boundary conditions in solving sparse linear equations to obtain the optimal module placement. Due to the total wire length determined by the module positions is the strong function of the preplaced I/O pad positions, the optimization of the I/O pad circular order and their assignment to the physical locations on the chip are attempted in the thesis. The proposed I/O pad assignment program is used as a ...

A Practical Parallel Algorithm For The Minimization Of KröNecker Reed-Muller Expansions, Paul John Gilliam

#### A Practical Parallel Algorithm For The Minimization Of KröNecker Reed-Muller Expansions, Paul John Gilliam

*Dissertations and Theses*

A number of recent developments has increased the desirability of using exclusive OR (XOR) gates in the synthesis of switching functions. This has, in turn, led naturally to an increased interest in algorithms for the minimization of Exclusive-Or Sum of Products (ESOP) forms. Although this is an active area of research, it is not nearly as developed as the traditional Sum of Products forms. Computer programs to find minimum ESOPs are not readily available and those that do exist are impractical to use as investigative tools because they are too slow and/or require too much memory. A practical tool ...

Parplum : A System For Evaluating Parallel Program Optimization Methods, Jingsong Fu

#### Parplum : A System For Evaluating Parallel Program Optimization Methods, Jingsong Fu

*Dissertations and Theses*

The diversity of application programs and parallel architectures makes the mapping problem complicated and hard to evaluate. The quality of mapping is machine and application dependent and varies due to inaccurate values of application and architecture characteristics.

A system for developing, applying and evaluating mappings must have four characteristics: (1) Simplicity: A mapping procedure can be evaluated by separately evaluating its submapping, so the complicated problem can be simplified. (2) Generality: A wide range of application programs and architectures can be easily represented and all mapping algorithms can be easily implemented. (3) Multifunctionality: all the mapping steps, application programs, target ...

Rivest-Shamir-Adelman Cryptosystem, Edward A. Fetzner

#### Rivest-Shamir-Adelman Cryptosystem, Edward A. Fetzner

*Theses, Dissertations & Honors Papers*

Cryptography, the art of writing secret messages, has been practiced for almost 3000 years. Two people have a message to communicate to each other , with a chance of an outside person intercepting the message before it reaches the receiver . Therefore, the message must be put through an encryption scheme to keep the intervening person from finding the true nature of the message . An encryption scheme is coding a message using an enciphering key and then decoding the coded message with a deciphering key .

A Survey Of Simultaneous Binary Multiplication, Joseph Larry Voyer

#### A Survey Of Simultaneous Binary Multiplication, Joseph Larry Voyer

*Retrospective Theses and Dissertations*

No abstract provided.