Engineering Commons^™

Reliability Techniques For Data Communication And Storage In Fpga-Based Circuits, Yubo Li

Theses and Dissertations

This dissertation studies the effects of radiation-induced single-event upsets (SEUs) on field-programmable gate array(FPGA)-based circuits. It analyzes and quantifies a special case in data communication, that is, the synchronization issue of signals when they are sent across clock domains in triple modular redundancy (TMR) circuits with the presence of SEUs. After demonstrating that synchronizing errors cannot be eliminated in such case, this dissertation continues to present novel synchronizer designs that can guarantee reliable synchronization of triplicated signals. Fault injection tests then show that the proposed synchronizers provide between 6 and 10 orders of magnitude longer mean time to failure (MTTF) …

Hardware-Software Co-Design, Acceleration And Prototyping Of Control Algorithms On Reconfigurable Platforms, Desta Kumsa Edosa

UNLV Theses, Dissertations, Professional Papers, and Capstones

Differential equations play a significant role in many disciplines of science and engineering. Solving and implementing Ordinary Differential Equations (ODEs) and partial Differential Equations (PDEs) effectively are very essential as most complex dynamic systems are modeled based on these equations. High Performance Computing (HPC) methodologies are required to compute and implement complex and data intensive applications modeled by differential equations at higher speed. There are, however, some challenges and limitations in implementing dynamic system, modeled by non-linear ordinary differential equations, on digital hardware. Modeling an integrator involves data approximation which results in accuracy error if data values are not considered …

Fpga Floor-Planning Impact On Implementation Results, Jaren Tyler Lamprecht

Theses and Dissertations

The field programmable gate array (FPGA) is an attractive computational platform for many applications because of its customizable nature and modest development cost, in terms of both time and money. As FPGAs scale to increased logical capacities, designers have increased flexibility. However, the FPGA placement problem becomes more difficult at increased sizes. Increasingly, designers are encouraged to structure designs hierarchically and floor-plan. Floor planning is a manual process which maps specified design submodules to selected physical regions of the FPGA device fabric. This thesis explores several of the effects that floor-planning has on submodules and the designs they comprise. A …

Air: Adaptive Dynamic Precision Iterative Refinement, Jun Kyu Lee

Doctoral Dissertations

In high performance computing, applications often require very accurate solutions while minimizing runtimes and power consumption. Improving the ratio of the number of logic gates implementing floating point arithmetic operations to the total number of logic gates enables greater efficiency, potentially with higher performance and lower power consumption. Software executing on the fixed hardware in Von-Neuman architectures faces limitations on improving this ratio, since processors require extensive supporting logic to fetch and decode instructions while employing arithmetic units with statically defined precision. This dissertation explores novel approaches to improve computing architectures for linear system applications not only by designing application-specific …

A Memory Controller For Fpga Applications, Bryan Jacob Hunter

Masters Theses

As designers and researchers strive to achieve higher performance, field-programmable gate arrays (FPGAs) become an increasingly attractive solution. As coprocessors, FPGAs can provide application specific acceleration that cannot be matched by modern processors. Most of these applications will make use of large data sets, so achieving acceleration will require a capable interface to this data. The research in this thesis describes the design of a memory controller that is both efficient and flexible for FPGA applications requiring floating point operations. In particular, the benefits of certain design choices are explored, including: scalability, memory caching, and configurable precision. Results are given …

Digital Graphic Equalizer Implemented Using An Fpga, Anthony Giardina

Electrical Engineering

A graphic equalizer is a device that adjusts the tonal quality of an audio signal. When sound is converted from a digital format to analog sound waves, there are amplification and transducing steps in-between the two formats. Common devices to perform these tasks are speakers, amplifiers, DACs, etc. Many of these devices exhibit a non-uniform frequency response over the range of human hearing. Thus, it is possible that certain frequency ranges of the audio signal will be amplified and others will be attenuated. To counteract this, an audio equalizer can be used to boost and attenuate certain frequency ranges within …

Extending The Hybridthread Smp Model For Distributed Memory Systems, Eugene Anthony Cartwright Iii

Graduate Theses and Dissertations

Memory Hierarchy is of growing importance in system design today. As Moore's Law allows system designers to include more processors within their designs, data locality becomes a priority. Traditional multiprocessor systems on chip (MPSoC) experience difficulty scaling as the quantity of processors increases. This challenge is common behavior of memory accesses in a shared memory environment and causes a decrease in memory bandwidth as processor numbers increase. In order to provide the necessary levels of scalability, the computer architecture community has sought to decentralize memory accesses by distributing memory throughout the system. Distributed memory offers greater bandwidth due to decoupled …

Design, Implementation, And Analysis Of A Time Of Arrival Measurement System For Rotating Machinery, Bryan Will Hayes

Masters Theses

The Non-contact Stress Measurement System (NSMS) acquires critical time of arrival data from multiple optical probes viewing a rotating piece of machinery, such as blades on a turbine engine rotor. The signal from each probe must be converted from light energy to an electrical signal, conditioned, and timed by a high speed counter to measure the time of arrival of the rotating machinery. This thesis describes, in detail, the design and analysis of the photo-detector electronics, analog signal conditioning electronics, and the timing electronics utilized in measuring the time of arrival. To measure the time of arrival with precision, the …

Limited Resource Feature Detection, Description, And Matching, Spencer G. Fowers

Theses and Dissertations

The aims of this research work are to develop a feature detection, description, and matching system for low-resource applications. This work was motivated by the need for a vision sensor to assist the flight of a quad-rotor UAV. This application presented a real-world challenge of autonomous drift stabilization using vision sensors. The initial solution implemented a basic feature detector and matching system on an FPGA. The research then pursued ways to improve the vision system. Research began with color feature detection, and the Color Difference of Gaussians feature detector was developed. CDoG provides better results than gray scale DoG and …

Understanding Design Requirements For Building Reliable, Space-Based Fpga Mgt Systems Based On Radiation Test Results, Kevin M. Ellsworth

Theses and Dissertations

Space-based computing applications often demand reliable, high-bandwidth communication systems. FPGAs with Mulit-Gigabit Transceivers (MGTs) provide an effective platform for such systems, but it is important that system designers understand the possible susceptibilities MGTs present to the system. Previous work has provided a foundation for understanding the susceptibility of raw FPGA MGTs but has fallen short of testing MGTs as part of a larger system. This work focuses on answering the questions MGT system designers need to know in order to build a reliable space-based MGT system. Two radiation tests were performed with a test architecture built on the Aurora protocol. …

Investigation On The Benefits Of Safety Margin Improvement In Candu Nuclear Power Plant Using An Fpga-Based Shutdown System, Jingke She

Electronic Thesis and Dissertation Repository

The relationship between response time and safety margin of CANadian Deuterium Uranium (CANDU) nuclear power plant (NPP) is investigated in this thesis. Implementation of safety shutdown system using Field Programmable Gate Array (FPGA) is explored. The fast data processing capability of FPGAs shortens the response time of CANDU shutdown systems (SDS) such that the impact of accident transient can be reduced. The safety margin, which is closely related to the reactor behavior in the event of an accident, is improved as a result of such a faster shutdown process.

Theoretical analysis based on neutron dynamic theory is carried out to …

Hardware And Software Fault-Tolerance Of Softcore Processors Implemented In Sram-Based Fpgas, Nathaniel Hatley Rollins

Theses and Dissertations

Softcore processors are an attractive alternative to using expensive radiation-hardened processors for space-based applications. Since they can be implemented in the latest SRAM-based FPGA technologies, they are fast, flexible and significantly less expensive. However, unlike ASIC-based processors, the logic and routing of a softcore processor are vulnerable to the effects of single-event upsets (SEUs). To protect softcore processors from SEUs, this dissertation explores the processor design-space for the LEON3 softcore processor implemented in a commercial SRAM-based FPGA. The traditional mitigation techniques of triple modular redundancy (TMR) and duplication with compare (DWC) and checkpointing provide reliability to a softcore processor at …

Using Hard Macros To Accelerate Fpga Compilation For Xilinx Fpgas, Christopher Michael Lavin

Theses and Dissertations

Field programmable gate arrays (FPGAs) offer an attractive compute platform because of their highly parallel and customizable nature in addition to the potential of being reconfigurable to any almost any desired circuit. However, compilation time (the time it takes to convert user design input into a functional implementation on the FPGA) has been a growing problem and is stifling designer productivity. This dissertation presents a new approach to FPGA compilation that more closely follows the software compilation model than that of the application specific integrated circuit (ASIC). Instead of re-compiling every module in the design for each invocation of the …