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Mobility Modeling And Simulation Of Soi Si1-X Gex P-Mosfet, Sida Zhou
Mobility Modeling And Simulation Of Soi Si1-X Gex P-Mosfet, Sida Zhou
Dissertations and Theses
With increasing demand for complex and faster circuits, CMOS technologies are progressing towards the deep-submicron level. Process complexity increases dramatically, and costly techniques are to be developed to create dense field isolation and shallow junctions. Silicon-On-Insulator (SOI) may solve some of these problems. On the other hand, strained Si1-x Gex layers have been successfully grown on Si substrates and demonstrated much higher hole mobility than bulk Si. This can be used to build high-mobility p-MOSFET with a buried Si1-x Gex channel. A high mobility p-MOSFET would improve both the circuit speed and the level of integration. …
Scaling Of The Silicon-On-Insulator Si And Si1-Xgex P-Mosfets, Marijan PeršUn
Scaling Of The Silicon-On-Insulator Si And Si1-Xgex P-Mosfets, Marijan PeršUn
Dissertations and Theses
Two-dimensional numerical simulation was used to study the scaling properties of SOI p-MOSFETs. Based on the design criteria for the threshold voltage and DIBL, a set of design curves for different designs was developed. Data for subthreshold slope, SCE and threshold voltage sensitivity to silicon film thickness are also given. Results show that short-channel effects can be controlled by increasing the doping level or by thinning the silicon film thickness. The first approach is more effective for p+ gate design with high body doping, while the second approach is much more effective for n+ gate design with low body doping. …