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Multi-Threshold Cmos Circuit Design Methodology From 2d To 3d, Ross Josiah Thian
Multi-Threshold Cmos Circuit Design Methodology From 2d To 3d, Ross Josiah Thian
Graduate Theses and Dissertations
A new and exciting approach in digital IC design in order to accommodate the Moore's law is 3D chip stacking. Chip stacking offers more transistors per chip, reduced wire lengths, and increased memory access bandwidths. This thesis demonstrates that traditional 2D design flow can be adapted for 3D chip stacking. 3D chip stacking has a serious drawback: heat generation. Die-on-die architecture reduces exposed surface area for heat dissipation. In order to reduce heat generation, a low power technique named Multi-Threshold CMOS (MTCMOS) was incorporated in this work. MTCMOS required designing a power management unit (to control when and which gates …
A Methodology For Implementing Rf Bists In Production Testing To Replace Rf Conventional Tests, Deepa Mannath
A Methodology For Implementing Rf Bists In Production Testing To Replace Rf Conventional Tests, Deepa Mannath
Graduate Theses and Dissertations
Production testing of Radio Frequency (RF) devices is challenging due to the complex nature of the tests that have to be performed to verify functionality. In this dissertation a methodology to replace the complex and expensive RF functional tests with defect-oriented Built-in Self Tests (BiSTs) is detailed. If a design has sufficient margin to RF specifications then RF tests can be replaced with structural tests using a new data analysis technique called quadrant analysis, which is presented. Data from the analysis of over one million production units of said System on Chip (SoC) is presented along with the results of …