Engineering Commons^™

Accelerating Reverse Engineering Image Processing Using Fpga, Matthew Joshua Harris

Browse all Theses and Dissertations

In recent decades, field programmable gate arrays (FPGAs) have evolved beyond simple, expensive computational components with minimal computing power to complex, inexpensive computational engines. Today, FPGAs can perform algorithmically complex problems with improved performance compared to sequential CPUs by taking advantage of parallelization. This concept can be readily applied to the computationally dense field of image manipulation and analysis. Processed on a standard CPU, image manipulation suffers with large image sets processed by highly sequential algorithms, but by carefully adhering to data dependencies, parallelized FPGA functions or kernels offer the possibility of significant improvement through threaded CPU functions. This thesis …

Leveraging Blockchain To Mitigate The Risk Of Counterfeit Microelectronics In Its Supply Chain, Aman Ali Pogaku

Browse all Theses and Dissertations

System on Chip (SoC) is the backbone component of the electronics industry nowadays. ASIC and FPGA-based SoCs are the two most popular methods of manufacturing SoCs. However, both ASIC and FPGA industries are plagued with risks of counterfeits due to the limitations in Security, Accountability, Complexity, and Governance of their supply chain management. As a result, the current practices of these microelectronics supply chain suffer from performance and efficiency bottlenecks. In this research, we are incorporating blockchain technology into the FPGA and ASIC microelectronic supply chain to help mitigate the risk of counterfeit microelectronics through a secure and decentralized solution …

Fpga-Based Ir Localization Sensor, Samuel I. Susanto

Browse all Theses and Dissertations

Pursuit-evasion scenarios are common in both natural and man-made systems. Often times, the pursuer and evader maneuver in response to each others actions using relative information based on the geometry of the agents and potential obstacles within the environment. The pursuer needs the target's bearing angle in order to plan a trajectory or path to capture it. We propose an FPGA-based infrared sensor array to detect up to 6 agents' bearing angles simultaneously. The final output of the sensor is the bearing angle of other agents. The sensor was tested and validated experimentally. Implementing the sensor and transmitter pair on …

Modern Digital Chirp Receiver: Theory, Design And System Integration, Stephen Ray Benson

Browse all Theses and Dissertations

Chirp signals can achieve a high range resolution without sacrificing SNR or maximum range, making them a strong candidate for use in radar and sonar applications. Chirp signals are also power efficient and resistant to interference, making them well suited for communication applications as well. The proposed digital high chirp rate receivers will showcase the use of digital instantaneous frequency measurement (IFM) devices for high chirp rate measurement. The receivers are paired with a high resolution time-of-arrival algorithm, capable of detecting the TOA and TOD of a pulse with an average error of less than 2ns. The high resolution pulse …

Dynamic Kernel Function For High-Speed Real-Time Fast Fourier Transform Processors, Yu-Heng George Lee

Browse all Theses and Dissertations

The fast Fourier transform (FFT) plays a critical role in many modern applications, such as acoustics, optics, telecommunications, wireless sensor networks, location sensing, patient monitoring, speech, signal detection, and image processing. The input dynamic range, data throughput rate, frequency resolution, bandwidth, design flexibility, hardware consumption, and power requirements for the various applications are vastly different, leading to significant research focusing on different aspects of FFT performance improvement.

The proposed dynamic kernel function uses an efficient fixed-point numerical representation of the twiddle factor and replaces the cumbersome multipliers with simple shift-and-add operations to enhance the data throughput rate for high-speed wideband …

Fpga Design Of A Hardware Efficient Pipelined Fft Processor, Ryan T. Bone

Browse all Theses and Dissertations

Digital receivers involve fast Fourier transform (FFT) computations that require a large amount of arithmetic operations. The implementation of a FFT processor is one of the most challenging parts in the realization of a wideband receiver and its hardware complexity is very high. Hence, kernel function FFT processors have been proposed to meet real-time processing requirements and to reduce hardware complexity by rounding the kernel function to predetermined kernel points so as to eliminate the multipliers and use only shifters and adders or subtractors. Because of the nonlinear nature of this approximation by the rounding errors, spurious responses are generated …

Improved Thresholding Technique For The Monobit Receiver, Jonathan Gordon Buck

Browse all Theses and Dissertations

Wideband digital receivers typically use a very high sampling rate to capture a signal for near real-time processing. Very robust digital techniques, like the Monobit FFT technique, have been developed to provide near real-time processing of captured timedomain signals. Most of these techniques trade accuracy for processing speed by approximating computationally complex mathematical operations. The approximation sometimes makes it difficult to detect multiple signals if the difference between their amplitudes is more than a few dB. This thesis presents a dynamic thresholding technique for multi-tone signal detection. The technique is based on setting an allowable ratio between the magnitude of …

Fpga Frequency Domain Based Gps Coarse Acquisition Processor Using Fft, Cyprian D. Sajabi

Browse all Theses and Dissertations

The Global Positioning System or GPS is a satellite based technology that has gained widespread use worldwide in civilian and military applications. Direct Sequence Spread spectrum (DSSS) is the method whereby the data transmitted by the satellite and received by user is kept secure, low power and relatively noise-immune. The first step required in the GPS operation is to perform a lock on the incoming signal, both with respect to time synchronization and frequency resolution. Because of the need for reduced time to lock and also reduced hardware, algorithms based in the frequency domain have been developed. These algorithms take …

A Field Programmable Gate Array Architecture For Two-Dimensional Partial Reconfiguration, Fei Wang

Browse all Theses and Dissertations

Reconfigurable machines can accelerate many applications by adapting to their needs through hardware reconfiguration. Partial reconfiguration allows the reconfiguration of a portion of a chip while the rest of the chip is busy working on tasks. Operating system models have been proposed for partially reconfigurable machines to handle the scheduling and placement of tasks. They are called OS4RC in this dissertation. The main goal of this research is to address some problems that come from the gap between OS4RC and existing chip architectures and the gap between OS4RC models and practical applications. Some existing OS4RC models are based on an …