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Analog Statistical Design For Manufacturability, Yu-Shan Wang

Dissertations and Theses

The manufacturing yield, overkill, and defect level limit the feasibility of analog circuits in SoCs. The conventional method of handling process and environmental variation is to assign a design margin such that the design meets specifications at several processes and environmental corners. However, checking only extreme corners limits performance in comparison to the more rigorous statistical approach of the computing manufacturing and quality figure of merit. The statistical approach requires transistor-level simulation of hundreds or even thousands of samples, not just a few corners, and thus is very time consuming.

This research offers a method for reducing the time required …