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Complete Design Methodology Of A Massively Parallel And Pipelined Memristive Stateful Imply Logic Based Reconfigurable Architecture, Kamela Choudhury Rahman
Complete Design Methodology Of A Massively Parallel And Pipelined Memristive Stateful Imply Logic Based Reconfigurable Architecture, Kamela Choudhury Rahman
Dissertations and Theses
Continued dimensional scaling of CMOS processes is approaching fundamental limits and therefore, alternate new devices and microarchitectures are explored to address the growing need of area scaling and performance gain. New nanotechnologies, such as memristors, emerge. Memristors can be used to perform stateful logic with nanowire crossbars, which allows for implementation of very large binary networks that can be easily reconfigured. This research involves the design of a memristor-based massively parallel datapath for various applications, specifically SIMD (Single Instruction Multiple Data) like architecture, and parallel pipelines. The dissertation develops a new model of massively parallel memristor-CMOS hybrid datapath architectures at …
The Design Of A Simple, Spiking Sparse Coding Algorithm For Memristive Hardware, Walt Woods
The Design Of A Simple, Spiking Sparse Coding Algorithm For Memristive Hardware, Walt Woods
Dissertations and Theses
Calculating a sparse code for signals with high dimensionality, such as high-resolution images, takes substantial time to compute on a traditional computer architecture. Memristors present the opportunity to combine storage and computing elements into a single, compact device, drastically reducing the area required to perform these calculations. This work focused on the analysis of two existing sparse coding architectures, one of which utilizes memristors, as well as the design of a new, third architecture that employs a memristive crossbar. These architectures implement either a non-spiking or spiking variety of sparse coding based on the Locally Competitive Algorithm (LCA) introduced by …