Engineering Commons^™

Equivalence Checking For High-Assurance Behavioral Synthesis, Kecheng Hao

Dissertations and Theses

The rapidly increasing complexities of hardware designs are forcing design methodologies and tools to move to the Electronic System Level (ESL), a higher abstraction level with better productivity than the state-of-the-art Register Transfer Level (RTL). Behavioral synthesis, which automatically synthesizes ESL behavioral specifications to RTL implementations, plays a central role in this transition. However, since behavioral synthesis is a complex and error-prone translation process, the lack of designers' confidence in its correctness becomes a major barrier to its wide adoption. Therefore, techniques for establishing equivalence between an ESL specification and its synthesized RTL implementation are critical to bring behavioral synthesis …

Extending Technology Roadmap Through Fuzzy Cognitive Map-Based Scenarios: The Case Of The Wind Energy Sector Of Pakistan, Muhammad Amer

Dissertations and Theses

In this modern era, energy is a key element required for sustainable development and prosperity of a society. Pakistan is an energy deficient country facing problems due to the shortage of over 4000 MW of electricity. The national energy sector is heavily dependent on imported fossil-fuel resources. The energy crisis is negatively affecting all economic and business activities, and it is widely recognized as a severe obstacle to growth and poverty reduction in the country. Establishment of wind farms can help to overcome the energy crisis.

In this research, a national level wind energy roadmap is developed through scenario planning. …

Just-In-Time Power Gating Of Gasp Circuits, Prachi Gulab Padwal

Dissertations and Theses

In modern integrated circuits, one way to reduce power consumption is to turn off power to parts of the circuit when those are idle. This method is called power gating. This thesis presents a state-preserving technique to achieve power savings in GasP family of asynchronous circuits by turning off the power when the circuit is idle. The power control logic turns on the power in anticipation of the receiving data. The power control logic turns off the power when the stage is idle either because it is empty or because the pipeline is clogged. The low logical effort of GasP …