Engineering Commons^™

A Low-Power, Low-Area 10-Bit Sar Adc With Length-Based Capacitive Dac, Zhili Pan

Department of Electrical and Computer Engineering: Dissertations, Theses, and Student Research

A 2.5 V single-ended 10-bit successive-approximation-register analog-to-digital converter (SAR ADC) based on the TSMC 65 nm CMOS process is designed with the goal of achieving low power consumption (33.63 pJ/sample) and small area (2874 µm^2 ). It utilizes a novel length-based capacitive digital-to-analog converter (CDAC) layout to achieve low total capacitance for power efficiency, and a custom static asynchronous logic to free the dependence on a high-frequency external clock source. Two test chips have been designed and the problems found through testing the first chip are analyzed. Multiple improved versions of the ADC with minor variations are implemented on the …

Etching Process Development For Sic Cmos, Weston Reed Renfrow

Graduate Theses and Dissertations

Silicon Carbide (SiC) is an exciting material that is growing in popularity for having qualities that make it a helpful semiconductor in extreme environments where silicon devices fail. The development of a SiC CMOS is in its infancy. There are many improvements that need to be made to develop this technology further. Photolithography is the most significant bottleneck in the etching process; it was studied and improved upon. Etching SiC can be a challenge with its reinforced crystal structure. Chlorine-based inductively coupled plasma (ICP) etching of intrinsic SiC and doped SiC, SiO2, and Silicon has been studied. A baseline chlorine …

Cmos Compatible Carbonization Of Polymer For Elctrochemical Sensors, Mohammad Aminul Haque

Doctoral Dissertations

Carbon-based electrodes that are integrable with CMOS readout electrodes possess great potential in a wide range of cutting-edge applications. The primary scientific contribution is the development of a processing sequence which can be implemented on CMOS chips to fabricate pyrolyzed carbon microelectrodes from 3D printed polymer microstructures to develop lab-on-CMOS monolithic electrochemical sensor systems. Specifically, optimized processing conditions to convert 3D printed polymer micro- and nano-structures to carbonized electrodes have been explored in order to obtain sensing electrodes for lab-on- CMOS electrochemical systems. Processing conditions have been identified, including a sequel of oxidative and inert atmosphere anneals to form pyrolyzed …

A Ringamp-Assisted, Output Capacitor-Less Analog Cmos Low-Dropout Voltage Regulator, Jordan Sangid

Doctoral Dissertations

Continued advancements in state-of-the-art integrated circuits have furthered trends toward higher computational performance and increased functionality within smaller circuit area footprints, all while improving power efficiencies to meet the demands of mobile and battery-powered applications. A significant portion of these advancements have been enabled by continued scaling of CMOS technology into smaller process node sizes, facilitating faster digital systems and power optimized computation. However, this scaling has degraded classic analog amplifying circuit structures with reduced voltage headroom and lower device output resistance; and thus, lower available intrinsic gain. This work investigates these trends and their impact for fine-grain Low-Dropout (LDO) …

Phase Noise Analyses And Measurements In The Hybrid Memristor-Cmos Phase-Locked Loop Design And Devices Beyond Bulk Cmos, Naheem Olakunle Adesina

LSU Doctoral Dissertations

Phase-locked loop (PLLs) has been widely used in analog or mixed-signal integrated circuits. Since there is an increasing market for low noise and high speed devices, PLLs are being employed in communications. In this dissertation, we investigated phase noise, tuning range, jitter, and power performances in different architectures of PLL designs. More energy efficient devices such as memristor, graphene, transition metal di-chalcogenide (TMDC) materials and their respective transistors are introduced in the design phase-locked loop.

Subsequently, we modeled phase noise of a CMOS phase-locked loop from the superposition of noises from its building blocks which comprises of a voltage-controlled oscillator, …

Cascading Cmos-Based Chaotic Maps For Improved Performance And Its Application In Efficient Rng Design, Partha Sarathi Paul, Maisha Sadia, Md Razuan Hossain, Barry Muldrey, Md Sakib Hasan

Faculty and Student Publications

We present a general framework for improving the chaotic properties of CMOS-based chaotic maps by cascading multiple maps in series. Along with two novel chaotic map topologies, we present the 45 $nm$ designs for four CMOS-based discrete-time chaotic map topologies. With the help of the bifurcation plot and three established entropy measures, namely, Lyapunov exponent, Kolmogorov entropy, and correlation coefficient, we present an extensive chaotic performance analysis on eight unique map circuits (two under each topology) to show that under certain constraints, the cascading scheme can significantly elevate the chaotic performance. The improved chaotic entropy benefits many security applications and …

The Design Of Cmos Front-End Amplifiers For Electrical Impedance Applications, Yueh-Ching Teng

Dartmouth College Ph.D Dissertations

Electrical Impedance Tomography (EIT) is a medical imaging methodology that does not need any kind of ionizing radiation. It is significantly cheaper and smaller than Computerized Tomography (CT) or Magnetic Resonance Imaging (MRI). These advantages make EIT particularly suitable for emerging applications like the continuous medical imaging and telemonitoring of organ function. Current bench-top EIT systems are bulky and require shielded cables to interface with measurement electrodes. The cable introduces parasitic capacitances which shunt the desired signals and degrade the accuracy of the measurements. A EIT system based on application-specific integrated circuits (ASICs) can reduce the parasitic and stray capacitance …