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A Five Micron, Self Aligned, Polysilicon Gate Cmos Process Design, John P. Scoopo

Journal of the Microelectronic Engineering Conference

The design of a five micron, polysilicon gate, CMOS process is discussed. A p-well approach was used with aoriented n-type substrate as the starting material. Calculations of the threshold adjustment dose and desired doping level of the p-well were based on a desired threshold voltage of -0.8 volts for the p-channel transistor and 0.8 volts for the n-channel device. The desired doping levels of the sources and drains were based on minimizing the parasitic resistances and capacitances associated with a MOS transistor. SUPREM II was used to determine the implant/drive cycles necessary to obtain the required doping profiles and to …