Engineering Commons^™

Hardware Trojan Detection Utilizing Graph Neural Networks And Structural Checking, Hunter James Nauman

Graduate Theses and Dissertations

The integrated circuit (IC) industry has experienced exponential growth, particularly in the complexity and scale of hardware designs. To sustain this growth, faster development cycles and cost-effective solutions have been the focus for many companies. One strategy to maintain this growth is through the incorporation of third-party intellectual property (IP) into the IC design process. Outsourcing the production of sub-components reduces development time and enables faster time-to-market, however, this approach also introduces the threat of Hardware Trojans. Hardware Trojans, defined as any malicious modification or addition to an IC, pose significant security risks due to their small size, low activation …

Deep Learning Frameworks For Accelerated Magnetic Resonance Image Reconstruction Without Ground Truths, Ibsa Kumara Jalata

Graduate Theses and Dissertations

Magnetic Resonance Imaging (MRI) is typically a slow process because of its sequential data acquisition. To speed up this process, MR acquisition is often accelerated by undersampling k-space signals and solving an ill-posed problem through a constrained optimization process. Image reconstruction from under-sampled data is posed as an inverse problem in traditional model-based learning paradigms. While traditional methods use image priors as constraints, modern deep learning methods use supervised learning with ground truth images to learn image features and priors. However, in some cases, ground truth images are not available, making supervised learning impractical. Recent data-centric learning frameworks such as …

Trojan Detection Expansion Of Structural Checking, Zachary Chapman

Graduate Theses and Dissertations

With the growth of the integrated circuit (IC) market, there has also been a rise in demand for third-party soft intellectual properties (IPs). However, the growing use of such Ips makes it easier for adversaries to hide malicious code, like hardware Trojans, into these designs. Unlike software Trojan detection, hardware Trojan detection is still an active research area. One proposed approach to this problem is the Structural Checking tool, which can detect hardware Trojans using two methodologies. The first method is a matching process, which takes an unknown design and attempts to determine if it might contain a Trojan by …

A Memory-Centric Customizable Domain-Specific Fpga Overlay For Accelerating Machine Learning Applications, Atiyehsadat Panahi

Graduate Theses and Dissertations

Low latency inferencing is of paramount importance to a wide range of real time and userfacing Machine Learning (ML) applications. Field Programmable Gate Arrays (FPGAs) offer unique advantages in delivering low latency as well as energy efficient accelertors for low latency inferencing. Unfortunately, creating machine learning accelerators in FPGAs is not easy, requiring the use of vendor specific CAD tools and low level digital and hardware microarchitecture design knowledge that the majority of ML researchers do not possess. The continued refinement of High Level Synthesis (HLS) tools can reduce but not eliminate the need for hardware-specific design knowledge. The designs …

Structural Checking Tool Restructure And Matching Improvements, Derek Taylor

Graduate Theses and Dissertations

With the rising complexity and size of hardware designs, saving development time and cost by employing third-party intellectual property (IP) into various first-party designs has become a necessity. However, using third-party IPs introduces the risk of adding malicious behavior to the design, including hardware Trojans. Different from software Trojan detection, the detection of hardware Trojans in an efficient and cost-effective manner is an ongoing area of study and has significant complexities depending on the development stage where Trojan detection is leveraged. Therefore, this thesis research proposes improvements to various components of the soft IP analysis methodology utilized by the Structural …

Non-Volatile Memory Adaptation In Asynchronous Microcontroller For Low Leakage Power And Fast Turn-On Time, Jean Pierre Thierry Habimana

Graduate Theses and Dissertations

This dissertation presents an MSP430 microcontroller implementation using Multi-Threshold NULL Convention Logic (MTNCL) methodology combined with an asynchronous non-volatile magnetic random-access-memory (RAM) to achieve low leakage power and fast turn-on. This asynchronous non-volatile RAM is designed with a Spin-Transfer Torque (STT) memory device model and CMOS transistors in a 65 nm technology. A self-timed Quasi-Delay-Insensitive 1 KB STT RAM is designed with an MTNCL interface and handshaking protocol. A replica methodology is implemented to handle write operation completion detection for long state-switching delays of the STT memory device. The MTNCL MSP430 core is integrated with the STT RAM to create …

An Fpga-Based Hardware Accelerator For The Digital Image Correlation Engine, Keaten Stokke

Graduate Theses and Dissertations

The work presented in this thesis was aimed at the development of a hardware accelerator for the Digital Image Correlation engine (DICe) and compare two methods of data access, USB and Ethernet. The original DICe software package was created by Sandia National Laboratories and is written in C++. The software runs on any typical workstation PC and performs image correlation on available frame data produced by a camera. When DICe is introduced to a high volume of frames, the correlation time is on the order of days. The time to process and analyze data with DICe becomes a concern when …

Hardware Ip Classification Through Weighted Characteristics, Brendan Mcgeehan

Graduate Theses and Dissertations

Today’s business model for hardware designs frequently incorporates third-party Intellectual Property (IP) due to the many benefits it can bring to a company. For instance, outsourcing certain components of an overall design can reduce time-to-market by allowing each party to specialize and perfect a specific part of the overall design. However, allowing third-party involvement also increases the possibility of malicious attacks, such as hardware Trojan insertion. Trojan insertion is a particularly dangerous security threat because testing the functionality of an IP can often leave the Trojan undetected. Therefore, this thesis work provides an improvement on a Trojan detection method known …

A Proposed Approach To Hybrid Software-Hardware Application Design For Enhanced Application Performance, Alex Shipman

Graduate Theses and Dissertations

One important aspect of many commercial computer systems is their performance; therefore, system designers seek to improve the performance next-generation systems with respect to previous generations. This could mean improved computational performance, reduced power consumption leading to better battery life in mobile devices, smaller form factors, or improvements in many areas. In terms of increased system speed and computation performance, processor manufacturers have been able to increase the clock frequency of processors up to a point, but now it is more common to seek performance gains through increased parallelism (such as a processor having more processor cores on a single …

Securing Soft Ips Against Hardware Trojan Insertion, Thao Phuong Le

Graduate Theses and Dissertations

Due to the increasing complexity of hardware designs, third-party hardware Intellectual Property (IP) blocks are often incorporated in order to alleviate the burden on hardware designers. However, the prevalence use of third-party IPs has raised security concerns such as Trojans inserted by attackers. Hardware Trojans in these soft IPs are extremely difficult to detect through functional testing and no single detection methodology has been able to completely address this issue. Based on a Register-Transfer Level (RTL) and gate-level soft IP analysis method named Structural Checking, this dissertation presents a hardware Trojan detection methodology and tool by detailing the implementation of …

Exploiting Hardware Abstraction For Parallel Programming Framework: Platform And Multitasking, Hongyuan Ding

Graduate Theses and Dissertations

With the help of the parallelism provided by the fine-grained architecture, hardware accelerators on Field Programmable Gate Arrays (FPGAs) can significantly improve the performance of many applications. However, designers are required to have excellent hardware programming skills and unique optimization techniques to explore the potential of FPGA resources fully. Intermediate frameworks above hardware circuits are proposed to improve either performance or productivity by leveraging parallel programming models beyond the multi-core era.

In this work, we propose the PolyPC (Polymorphic Parallel Computing) framework, which targets enhancing productivity without losing performance. It helps designers develop parallelized applications and implement them on FPGAs. …

A Hybrid Partially Reconfigurable Overlay Supporting Just-In-Time Assembly Of Custom Accelerators On Fpgas, Zeyad Tariq Aklah

Graduate Theses and Dissertations

The state of the art in design and development flows for FPGAs are not sufficiently mature to allow programmers to implement their applications through traditional software development flows. The stipulation of synthesis as well as the requirement of background knowledge on the FPGAs' low-level physical hardware structure are major challenges that prevent programmers from using FPGAs. The reconfigurable computing community is seeking solutions to raise the level of design abstraction at which programmers must operate, and move the synthesis process out of the programmers' path through the use of overlays. A recent approach, Just-In-Time Assembly (JITA), was proposed that enables …

Prevention Of Drone Jamming Using Hardware Sandboxing, Joshua Mead

Graduate Theses and Dissertations

In this thesis, we concern ourselves with the security of drone systems under jamming-based attacks. We explore a relatively new concept we previously devised, known as hardware sandboxing, to provide runtime monitoring of boundary signals and isolation through resource virtualization for non-trusted system-on-chip (SoC) components. The focus of this thesis is the synthesis of this design and structure with the anti-jamming, security needs of drone systems. We utilize Field Programmable Gate Array (FPGA) based development and target embedded Linux for our hardware sandbox and drone hardware/software system.

We design and implement our working concept on the Digilent Zybo FPGA, which …

Hardware Trojan Detection Via Golden Reference Library Matching, Lucas Weaver

Graduate Theses and Dissertations

Due to the proliferation of hardware Trojans in third party Intellectual Property (IP) designs, the issue of hardware security has risen to the forefront of computer engineering. Because of the miniscule size yet devastating effects of hardware Trojans, few detection methods have been presented that adequately address this problem facing the hardware industry. One such method with the ability to detect hardware Trojans is Structural Checking. This methodology analyzes a soft IP at the register-transfer level to discover malicious inclusions. An extension of this methodology is presented that expands the list of signal functionalities, termed assets, in addition to introducing …

Optimizing Performance And Scalability On Hybrid Mpsocs, Hongyuan Ding

Graduate Theses and Dissertations

Hardware accelerators are capable of achieving significant performance improvement. But design- ing hardware accelerators lacks the flexibility and the productivity. Combining hardware accelerators with multiprocessor system-on-chip (MPSoC) is an alternative way to balance the flexibility, the productivity, and the performance. However, without appropriate programming model it is still a challenge to achieve parallelism on a hybrid (MPSoC) with with both general-purpose processors and dedicated accelerators. Besides, increasing computation demands with limited power budget require more energy-efficient design without performance degradation in embedded systems and mobile computing platforms. Reconfigurable computing with emerging storage technologies is an alternative to enable the optimization …