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An Empirical Study And Modeling On Selected Analog Circuits Using A Metal-Ferroelectric-Semiconductor Field Effect Transistor, Mitchell Ryan Hunt

Theses

No abstract provided.

Schottky Field Effect Transistors And Schottky Cmos Circuitry, Reinaldo Vega

Theses

It was the primary goal (and result) of the presented work to empirically demonstrate CMOS operation (i.e., inverter transfer characteristics) using metallic/Schottky source/drain MOSFETs (SFETs - Schottky Field Effect Transistors) fabricated on silicon-on-insulator (SOI) substrates - a first-ever in the history of SFET research. Due to its candidacy for present and future CMOS technology, many different research groups have explored different SFET architectures in an effort to maximize performance. In the presented work, an architecture known as a "bulk switching" SFET was fabricated using an implant-to-silicide (ITS) technique, which facilitates a high degree of Schottky barrier lowering and therefore an …

Electrophoretic Deposition Of Ferrite, Cody Washburn

Theses

The ability to integrate a material with a high permeability on chip, allows for magnetically coupled circuits and structures to be designed and incorporated along side CMOS circuitry. Devices ranging from A.C. transformers to magnetically driven MEMS structures can be designed and fabricated. Desirable characteristics of magnetic cores for integrated inductors and transformers are first high saturation flux in order to obtain high saturation current; high permeability to obtain high inductance; high resistivity to reduce eddy current loss at high frequencies and compatible deposition and patterning processes. High frequency magnetic materials are oxide based ceramics and are therefore difficult to …

Development Of Deep Submicron Cmos Process For Fabrication Of High Performance 0.25 Nm Transistors, Michael Aquilino

Theses

An advanced process for fabrication of 0.25 μm CMOS transistors has been demonstrated. This process is designed for transistors with Lpoly = 0.25 μm and Leffective = 0.2 um on 150 mm (6”) silicon wafers. Devices with Leffective of 0.2 um and smaller have been tested and found operational. A 0.25 um NMOS transistor with drain current of 177 μA/μm at VG=VD=2.5 V and a PMOS transistor with drain current of 131 μA/μm at VG=VD=-2.5 V are reported. The threshold voltages are 1.0 V for the NMOS and -0.735 V for the PMOS transistors. These 0.25 um NMOS and PMOS …

0.18?M High Performance Cmos Process Optimization, Zeki Gurcan

Theses

Complementary metal oxide semiconductor (CMOS) is the most widely used discrete structure in the semiconductor sector. Low static power consumption, full-rail high/low voltage transfer characteristics as well as its ease of scaling creates the perfect combination for the high performance integrated circuits (IC). Today’s challenging semiconductor industry profile brings the deadlines earlier than expected as a result of the shorter time-to- market plans as well as limited lifetime on sophisticated ICs. Process optimization for manufacturability is one of the most challenging issues in the semiconductor industry since the adoption of the sub-micron CMOS technology. Process technologies often times gets released …

Characterisation, Modelling And Performance Evaluation Of Cmos Integrated Rf-Mems Multielectrode Tunable Capacitor, Zbigniew Olszewski

Theses

The circuits used in telecommunications are made of two types of components; active integrated circuits that have continuously been improved together with the evolution of the Si technology and off-chip and on-chip passive components. The latter did not profit from much development and now constitute the bottleneck for further integration of RF (Radio Frequency) integrated circuits. MicroElectroMechanical Systems (MEMS) is rapidly emerging as an enabling technology to yield a new generation of high performance components to replace off-chip (not integrated) and on-chip (poor performance) counterparts. The RF components (RF-MEMS) that can be fabricated with MEMS technology are mainly the resonator, …

Power Supply Noise Coupling In A Standard Voltage Reference Circuit, Murat Ozbas

Theses

Power supply noise coupling represents a challenge in the design of current and future analog and mixed-signal circuits and systems. In this thesis, power supply noise coupling is analyzed at the circuit level. As a representative study, power supply noise coupling in a voltage reference is studied. The precision of a voltage reference circuit is critical to the performance of other analog and RF circuits. Therefore, there is much value in developing a deeper understanding of the mechanisms through which power supply noise coupling occurs in this fundamental analog and RF system building block. A model representing the amount of …

Development Of A Fully-Depleted Thin-Body Finfet Process, Branislav Curanovic

Theses

The goal of this work is to develop the processes needed for the demonstration of a fully-depleted (FD) thin-body fin field effect transistor (FinFET). Recognized by the 2003 International Technology Roadmap for Semiconductors as an emerging non-classical CMOS technology, FinFETs exhibit high drive current, reduced short-channel effects, an extreme scalability to deep submicron regimes. The approach used in this study will build on previous FinFET research, along with new concepts and technologies. The critical aspects of this research are: (1) thin body creation using spacer etchmasks and oxidation/etchback schemes, (2) use of an oxynitride gate dielectric, (3) silicon crystal orientation …

The Integration Of Si-Based Resonant Interband, Stephen Sudirgo

Theses

eports the first demonstration of the integration of CMOS and Si/SiGe resonant interband tunnel diode (RITD). In Si-based material, recent breakthrough in Si/SiGe RITD grown using molecular beam epitaxy (MBE) made the integration with CMOS possible. The resultant devices enabled the realization of RITD CMOS circuitry, and a NMOS-RITD MOBILE latch was demonstrated in Si, all enabling digital and ternary circuit design for density storage

Design Of Low Phase Drift Cmos Frequency Synthesisers, Cyril Patrick Hervé Florent Lahuec

Theses

This thesis presents a methodology for the development of high performance video clock synthesisers that have high (2000) input to output clock multiplication ratios. The synthesisers are required to be compatible with standard CMOS technologies and they must exhibit very low drift between their input and output clocks.

The methodology used borrows techniques established for RF synthesisers in the GHz range. In the RF domain there are significant constraints on spectral spread and because of this there has been significant interest in phase noise generated by intrinsic device noise. Simple and accurate models were developed that help understand the up …

Flash Adc Using 2Μm Cmos P-Well Technology : Design And Test, Joseph E. Levinson

Theses

This thesis describes the design, implementation and test for a new CMOS analog-to-digital converter IC chip. In designing the analog-to-digital converter in this thesis a radically different comparator design that is only available with CMOS logic. The design utilizes a single CMOS inverter as an ultra-high gain amplifier. This approach reduces the circuit dependence upon matching of the transistors similar to the traditional method. This new design requires less area since the comparator utilizes fewer transistors.

Flash analog-to-digital converters use 2" - 1 comparators to do a single conversion where n is the number of bits used. These comparators are …

Three Dimensional Magnetic Field Sensors And Array In Bicmos Technology, Bingda Wang

Theses

This thesis presents new designs of three dimensional magnetic field sensors in BiCMOS technology. The detailed design of the merged structure device by common diffusion and the high gain transduction circuit are presented. The merged structure has the advantage of less area, less external contacts and less parasitic capacitance. Cross-sensitivity is also eliminated by employing the merged structure. Three active on-chip loads are introduced to improve the sensitivity. The SPICE simulation results show that when a relative change in current ΔI/I is 0.001, about 13.6 mV and 8.5mV can be detected at the output in X(or Y) and Z directions, …

A Transistor Delay Model Based On Charge Conservation, Bharatsingh K. Bisen

Theses

Delay information of a circuit is often used in the areas of timing verification, timing analysis, race detection and circuit optimization. Given a circuit its delay can be estimated by various simulation techniques. SPICE is one of the simulation techniques, but it is seen that with the increase in the complexity of the circuit the SPICE circuit simulation technique to obtain delay information become cumbersome and computationally too expensive. So as to overcome the above disadvantages of the circuit simulation technique to obtain delay information various timing delay models were developed. However general survey of most of these timing delay …

Investigation Of Different Cmos Dram Sense Amplifier Configurations In Vlsi, Bihju Chiu

Theses

Sense amplifiers are particularly difficult circuits to design. In this work, only CMOS sense amplifiers are considered. There are typically two configurations of CMOS sense amplifiers: the cross-connected flip flop configuration and the current-mirror configuration. They are widely used nowadays with various modifications. These improved configurations are simulated and optimized with SPICE package, and their relative performances are also compared in this thesis.