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Charge Storage And Decay In High Temperature Insulating Materials., Mohamed Abdulbari A. Sussi
Charge Storage And Decay In High Temperature Insulating Materials., Mohamed Abdulbari A. Sussi
Electronic Theses and Dissertations
This dissertation deals with the studies of charge storage and decay in aromatic and composite polyamide materials for the first time, along with an extended study of the conduction currents in Teflon (PTFE) at higher ranges of applied electric fields and 2 temperatures, where the data obtained fills the gap in the published literature. Different experimental techniques are employed to identify the mechanisms responsible for conduction currents, charge storage, and decay in aromatic and composite polyamides. The insulating materials tested during the course of this dissertation are chosen because of their engineering importance and lack of published literature on them. …
Bicmos Implementation On Dsp Arithmetic Blocks., Henry Hin Hai. Chan
Bicmos Implementation On Dsp Arithmetic Blocks., Henry Hin Hai. Chan
Electronic Theses and Dissertations
This thesis presents an improved VLSI architecture to perform different arithmetic operations, multiplication, division and square rooting, along with addition and subtraction. The architecture is highly regular, requires only three control bits to choose among five different operations. Through the use of a redundant binary number system and pipelining, the execution time for each operation is identical and is independent of the wordsize of the array. Moreover, the improved architecture is capable of being implemented using the dynamic switching tree technique. Finally, the improved architecture has been designed utilizing a 0.8 micron BiCMOS technology and has a throughput rate of …
Image Coding For Monochrome And Colour Images., Napiluon Petrus Shlimon
Image Coding For Monochrome And Colour Images., Napiluon Petrus Shlimon
Electronic Theses and Dissertations
This work is an investigation of different algorithms to implement a lossy compression scheme. Special emphasis was focused on the quantization techniques. A CODEC (coder/decoder) based on a scheme proposed for standardization by a group known as JPEG (Joint Photographic Experts Group) was developed. Finally, a new decoding approach was developed, based on modifying the concepts of transition table used in compilers to break a binary string into variable length codes. The JPEG algorithm works in sequential mode by dividing the image into small blocks of 8 x 8 pixels. Each block is compressed separately by processing it through an …
Dynamic Logic Synthesis With Application To Self-Timed Pipelines., Hong Ming. Chan
Dynamic Logic Synthesis With Application To Self-Timed Pipelines., Hong Ming. Chan
Electronic Theses and Dissertations
This thesis describes a new method of designing multiple output dynamic logic suitable for an automatic synthesis procedure. A new cascode voltage switch logic synthesis method is derived with examples demonstrating the procedures. The procedures are summarized into 3 reduction rules. This method is modified to synthesize multiple output domino logic. A companion algorithm for handling "Don't care cases" is also developed. Another algorithm for transforming a non-planar circuit into a planar circuit for use in automatic layout synthesis is presented. An alternate method of realizing cascode voltage switch logic is developed. It is a semi-custom cell design method. The …
Pipelined And Trainable Architectures For Multi-Layer Neural Networks., Navid. Yazdi
Pipelined And Trainable Architectures For Multi-Layer Neural Networks., Navid. Yazdi
Electronic Theses and Dissertations
Multi-layer neural networks have a great learning ability and important applications. Hardware implementation of these networks are needed to exploit their full potential. In this thesis, various VLSI architectures for multi-layer neural networks are introduced. These architectures apply a hybrid digital/analog design methodology. The first architecture utilizes external digital weight memory and is trained with the aid of a host computer. The presented building blocks for this architecture are general. They are designed and implemented in a standard 1.2$\mu$ CMOS technology. Furthermore, two new general low cost pipelined architectures are introduced. They are independent of the internal architecture of each …