Digital Commons Network^™

Charge Injection And Clock Feedthrough, Jonathan Yu

Master's Theses

Turning off a transistor introduces an error voltage in switched-capacitor circuits. Circuits such as analog-to-digital converters (ADC), digital-to-analog converters (DAC), and CMOS image sensor pixels are limited in performance due to the effects known as charge injection and clock feedthrough. Charge injection occurs in a switched-capacitor circuit when the transistor turns off and disperses channel charge into the source and drain. The source, which is the sampling capacitor, experiences an error in the sampled voltage due to the incoming channel charge. Simultaneously, the coupling due to gate-source overlap capacitance also contributes to the total error voltage, which is known as …

Improvement Of A Propagation Delay Model For Cmos Digital Logic Circuits, Rodger Lawrence Stamness

Master's Theses

Propagation delay models, for CMOS Digital Circuits, provide an initial design solution for Integrated Circuits. Resources, both monetary and manpower, constrain the design process, leading to the need for a more accurate entry point further along in the design cycle. By verifying an existing propagation delay method, and its resulting delay model, calibration for any given process technology can be achieved. Literature reviews and detailed analysis of each step in the model development allow for greater understanding of each contributing parameter, and ultimately, adjustments to the model calibration result in a more accurate analytical model. An existing model was verified …

Partition Noise Extraction Using Tcad Simulations, Carol Cui Lan Lin

Master's Theses

As Complementary Metal Oxide Semiconductor (CMOS) technology scales down,

partition noise may start to play a bigger role in reducing the signal-to-noise ratio (SNR)

in sample-and-hold circuits and other capacitive sensing circuits that reset the voltage

across a capacitor. Previous studies on partition noise lack a reliable and accurate

measurement method to quantify partition noise. In our study, we have developed a

method using Technology Computer Aided Design (TCAD) simulations to estimate

partition noise. Through simulation, we determined the transistor dimensions and sense

capacitance required to measure partition noise. Furthermore, we designed a test circuit

based on our simulation results …