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Electrophoretic Deposition Of Ferrite, Cody Washburn
Electrophoretic Deposition Of Ferrite, Cody Washburn
Theses
The ability to integrate a material with a high permeability on chip, allows for magnetically coupled circuits and structures to be designed and incorporated along side CMOS circuitry. Devices ranging from A.C. transformers to magnetically driven MEMS structures can be designed and fabricated. Desirable characteristics of magnetic cores for integrated inductors and transformers are first high saturation flux in order to obtain high saturation current; high permeability to obtain high inductance; high resistivity to reduce eddy current loss at high frequencies and compatible deposition and patterning processes. High frequency magnetic materials are oxide based ceramics and are therefore difficult to …
Schottky Field Effect Transistors And Schottky Cmos Circuitry, Reinaldo Vega
Schottky Field Effect Transistors And Schottky Cmos Circuitry, Reinaldo Vega
Theses
It was the primary goal (and result) of the presented work to empirically demonstrate CMOS operation (i.e., inverter transfer characteristics) using metallic/Schottky source/drain MOSFETs (SFETs - Schottky Field Effect Transistors) fabricated on silicon-on-insulator (SOI) substrates - a first-ever in the history of SFET research. Due to its candidacy for present and future CMOS technology, many different research groups have explored different SFET architectures in an effort to maximize performance. In the presented work, an architecture known as a "bulk switching" SFET was fabricated using an implant-to-silicide (ITS) technique, which facilitates a high degree of Schottky barrier lowering and therefore an …
Development Of Deep Submicron Cmos Process For Fabrication Of High Performance 0.25 Nm Transistors, Michael Aquilino
Development Of Deep Submicron Cmos Process For Fabrication Of High Performance 0.25 Nm Transistors, Michael Aquilino
Theses
An advanced process for fabrication of 0.25 μm CMOS transistors has been demonstrated. This process is designed for transistors with Lpoly = 0.25 μm and Leffective = 0.2 um on 150 mm (6”) silicon wafers. Devices with Leffective of 0.2 um and smaller have been tested and found operational. A 0.25 um NMOS transistor with drain current of 177 μA/μm at VG=VD=2.5 V and a PMOS transistor with drain current of 131 μA/μm at VG=VD=-2.5 V are reported. The threshold voltages are 1.0 V for the NMOS and -0.735 V for the PMOS transistors. These 0.25 um NMOS and PMOS …