Digital Commons Network^™

A 32-Mw 320-Mhz Continuous-Time Complex Delta-Sigma Adc For Multi-Mode Wireless-Lan Receivers, Jesus Arias, Peter Kiss, Vladimir Prodanov, Vito Boccuzzi, Mihai Banu, David Bisbal, Jacinto San Pablo, Luis Quintanilla, Juan Barbolla

Electrical Engineering

We present an experimental continuous-time complex delta-sigma multi-bit modulator, implemented in standard 0.25-μm CMOS technology and meeting all major requirements for application in IEEE 802.11a/b/g wireless LAN receivers. The clock frequency is 320 MHz, producing an oversampling ratio of 16 for 20 MHz channel bandwidths. The modulator supports two operation modes for zero-IF and low-IF receiver architectures respectively, requires a single 2.5-V power supply, and dissipates only 32 mW of power. The measured peak signal-to-noise ratio is 55 dB. Further experimental results using sine-wave and OFDM test signals are also presented