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Signal Probabilities In And-Or Trees, Lester Lipsky, Sharad C. Seth
Signal Probabilities In And-Or Trees, Lester Lipsky, Sharad C. Seth
School of Computing: Faculty Publications
In this paper, we consider a class of AND-OR tree circuits and study their response to random-pattern inputs as the depth of the tree is allowed to increase indefinitely. Each binary input of a circuit is independently chosen to be one (zero) with probability x (1 - x). The logic of the circuit determines the probability of success (one) at the output as a monotonically increasing S-shaped function of x called the probability transfer function. The probability transfer function of an AND-OR tree is shown to have just one interior fixed point (w.r.t. changes in depth of …
Design Of Parity Testable Combinational Circuits, Bhargab B. Bhattacharya, Sharad C. Seth
Design Of Parity Testable Combinational Circuits, Bhargab B. Bhattacharya, Sharad C. Seth
School of Computing: Faculty Publications
The parity testability of a single output is related to its partition in terms of maximal supergates and then a scheme is proposed for making an untestable circuit parity testable by augmenting its maximal supergates. Only a small amount of extra logic and a single external test-mode pin is required to complete the design. The test procedure is simple and the hardware overhead is low.
A Theory Of Testability With Application To Fault Coverage Analysis, Sharad C. Seth, Vishwani Agrawal, Hassan Farhat
A Theory Of Testability With Application To Fault Coverage Analysis, Sharad C. Seth, Vishwani Agrawal, Hassan Farhat
School of Computing: Faculty Publications
When test vectors are applied to a circuit, the fault coverage increases. The rate of increase, however, could be circuit-dependent. In fact, the actual rise of fault coverage depends on the characteristics of vectors, as well as, on the circuit. The paper shows that the average fault coverage can be computed from circuit testability. A relationship between fault coverage and circuit testability is derived. The mathematical formulation allows computation of coverage for deterministic and random vectors. Applications of this analysis include: determination of circuit testability from fault simulation, coverage prediction from testability analysis, prediction of test length, and test generation …
Testability Analysis Of Synchronous Sequential Circuits Based On Structural Data, Raghu V. Hudli, Sharad C. Seth
Testability Analysis Of Synchronous Sequential Circuits Based On Structural Data, Raghu V. Hudli, Sharad C. Seth
School of Computing: Faculty Publications
Bounds on test sequence length can be used as a testability measure. We give a procedure to compute the upper bound on test sequence length for an arbitrary sequential circuit. We prove that the bound is exact for a certain class of circuits. Three design rules are specified to yield circuits with lower test sequence bounds.