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Sram Compiler For Automated Memory Layout Supporting Multiple Transistor Process Technologies, Brandon Hilgers

Master's Theses

This research details the design of an SRAM compiler for quickly creating SRAM blocks for Cal Poly integrated circuit (IC) designs. The compiler generates memory for two process technologies (IBM 180nm cmrf7sf and ON Semiconductor 600nm SCMOS) and requires a minimum number of specifications from the user for ease of use, while still offering the option to customize the performance for speed or area of the generated SRAM cell. By automatically creating SRAM arrays, the compiler saves the user time from having to layout and test memory and allows for quick updates and changes to a design. Memory compilers with …

Application-Specific Memory Subsystems, Joseph George Wingbermuehle

McKelvey School of Engineering Theses & Dissertations

The disparity in performance between processors and main memories has

led computer architects to incorporate large cache hierarchies in

modern computers. These cache hierarchies are designed to be

general-purpose in that they strive to provide the best possible

performance across a wide range of applications. However, such a memory

subsystem does not necessarily provide the best possible performance for

a particular application.

Although general-purpose memory subsystems are desirable when the

work-load is unknown and the memory subsystem must remain fixed,

when this is not the case a custom memory subsystem may be beneficial.

For example, in an application-specific integrated circuit …