Open Access. Powered by Scholars. Published by Universities.®
Articles 1 - 4 of 4
Full-Text Articles in Entire DC Network
Transient Safe Operating Area (Tsoa) For Esd Applications, Slavica Malobabic
Transient Safe Operating Area (Tsoa) For Esd Applications, Slavica Malobabic
Electronic Theses and Dissertations
A methodology to obtain design guidelines for gate oxide input pin protection and high voltage output pin protection in Electrostatic Discharge (ESD) time frame is developed through measurements and Technology Computer Aided Design (TCAD). A set of parameters based on transient measurements are used to define Transient Safe Operating Area (TSOA). The parameters are then used to assess effectiveness of protection devices for output and input pins. The methodology for input pins includes establishing ESD design targets under Charged Device Model (CDM) type stress in low voltage MOS inputs. The methodology for output pins includes defining ESD design targets under …
Study Of Esd Effects On Rf Power Amplifiers, Raju, Divya Narasimha
Study Of Esd Effects On Rf Power Amplifiers, Raju, Divya Narasimha
Electronic Theses and Dissertations
Today, ESD is a major consideration in the design and manufacture of ICs. ESD problems are increasing in the electronics industry because of the increasing trend toward higher speed and smaller device sizes. There is growing interest in knowing the effects of ESD protection circuit on the performance of semiconductor integrated circuits (ICs) because of the impact it has on core RF circuit performance. This study investigated the impact of ESD protection circuit on RF Power amplifiers. Even though ESD protection for digital circuits has been known for a while, RF-ESD is a challenge. From a thorough literature search on …
Design Of Silicon Controlled Rectifers Sic] For Robust Electrostatic Discharge Protection Applications, Zhiwei Liu
Design Of Silicon Controlled Rectifers Sic] For Robust Electrostatic Discharge Protection Applications, Zhiwei Liu
Electronic Theses and Dissertations
Electrostatic Discharge (ESD) phenomenon happens everywhere in our daily life. And it can occurs through the whole lifespan of an Integrated Circuit (IC), from the early wafer fabrication process, extending to assembly operation, and finally ending at the user‟s site. It has been reported that up to 35% of total IC field failures are ESD-induced, with estimated annual costs to the IC industry running to several billion dollars. The most straightforward way to avoid the ICs suffering from the threatening of ESD damages is to develop on-chip ESD protection circuits which can afford a robust, low-impedance bypassing path to divert …
Design Of Low-Capacitance And High-Speed Electrostatic Discharge (Esd) Devices For Low-Voltage Protection Applications, You Li
Electronic Theses and Dissertations
Electrostatic discharge (ESD) is defined as the transfer of charge between bodies at different potentials. The electrostatic discharge induced integrated circuit damages occur throughout the whole life of a product from the manufacturing, testing, shipping, handing, to end user operating stages. This is particularly true as microelectronics technology continues shrink to nano-metric dimensions. The ESD related failures is a major IC reliability concern and results in a loss of millions dollars to the semiconductor industry each year. Several ESD stress models and test methods have been developed to reproduce the real world ESD discharge events and quantify the sensitivity of …