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Reliability Techniques For Data Communication And Storage In Fpga-Based Circuits, Yubo Li
Reliability Techniques For Data Communication And Storage In Fpga-Based Circuits, Yubo Li
Theses and Dissertations
This dissertation studies the effects of radiation-induced single-event upsets (SEUs) on field-programmable gate array(FPGA)-based circuits. It analyzes and quantifies a special case in data communication, that is, the synchronization issue of signals when they are sent across clock domains in triple modular redundancy (TMR) circuits with the presence of SEUs. After demonstrating that synchronizing errors cannot be eliminated in such case, this dissertation continues to present novel synchronizer designs that can guarantee reliable synchronization of triplicated signals. Fault injection tests then show that the proposed synchronizers provide between 6 and 10 orders of magnitude longer mean time to failure (MTTF) …
Fpga Floor-Planning Impact On Implementation Results, Jaren Tyler Lamprecht
Fpga Floor-Planning Impact On Implementation Results, Jaren Tyler Lamprecht
Theses and Dissertations
The field programmable gate array (FPGA) is an attractive computational platform for many applications because of its customizable nature and modest development cost, in terms of both time and money. As FPGAs scale to increased logical capacities, designers have increased flexibility. However, the FPGA placement problem becomes more difficult at increased sizes. Increasingly, designers are encouraged to structure designs hierarchically and floor-plan. Floor planning is a manual process which maps specified design submodules to selected physical regions of the FPGA device fabric. This thesis explores several of the effects that floor-planning has on submodules and the designs they comprise. A …
Limited Resource Feature Detection, Description, And Matching, Spencer G. Fowers
Limited Resource Feature Detection, Description, And Matching, Spencer G. Fowers
Theses and Dissertations
The aims of this research work are to develop a feature detection, description, and matching system for low-resource applications. This work was motivated by the need for a vision sensor to assist the flight of a quad-rotor UAV. This application presented a real-world challenge of autonomous drift stabilization using vision sensors. The initial solution implemented a basic feature detector and matching system on an FPGA. The research then pursued ways to improve the vision system. Research began with color feature detection, and the Color Difference of Gaussians feature detector was developed. CDoG provides better results than gray scale DoG and …
Understanding Design Requirements For Building Reliable, Space-Based Fpga Mgt Systems Based On Radiation Test Results, Kevin M. Ellsworth
Understanding Design Requirements For Building Reliable, Space-Based Fpga Mgt Systems Based On Radiation Test Results, Kevin M. Ellsworth
Theses and Dissertations
Space-based computing applications often demand reliable, high-bandwidth communication systems. FPGAs with Mulit-Gigabit Transceivers (MGTs) provide an effective platform for such systems, but it is important that system designers understand the possible susceptibilities MGTs present to the system. Previous work has provided a foundation for understanding the susceptibility of raw FPGA MGTs but has fallen short of testing MGTs as part of a larger system. This work focuses on answering the questions MGT system designers need to know in order to build a reliable space-based MGT system. Two radiation tests were performed with a test architecture built on the Aurora protocol. …
Hardware And Software Fault-Tolerance Of Softcore Processors Implemented In Sram-Based Fpgas, Nathaniel Hatley Rollins
Hardware And Software Fault-Tolerance Of Softcore Processors Implemented In Sram-Based Fpgas, Nathaniel Hatley Rollins
Theses and Dissertations
Softcore processors are an attractive alternative to using expensive radiation-hardened processors for space-based applications. Since they can be implemented in the latest SRAM-based FPGA technologies, they are fast, flexible and significantly less expensive. However, unlike ASIC-based processors, the logic and routing of a softcore processor are vulnerable to the effects of single-event upsets (SEUs). To protect softcore processors from SEUs, this dissertation explores the processor design-space for the LEON3 softcore processor implemented in a commercial SRAM-based FPGA. The traditional mitigation techniques of triple modular redundancy (TMR) and duplication with compare (DWC) and checkpointing provide reliability to a softcore processor at …
Using Hard Macros To Accelerate Fpga Compilation For Xilinx Fpgas, Christopher Michael Lavin
Using Hard Macros To Accelerate Fpga Compilation For Xilinx Fpgas, Christopher Michael Lavin
Theses and Dissertations
Field programmable gate arrays (FPGAs) offer an attractive compute platform because of their highly parallel and customizable nature in addition to the potential of being reconfigurable to any almost any desired circuit. However, compilation time (the time it takes to convert user design input into a functional implementation on the FPGA) has been a growing problem and is stifling designer productivity. This dissertation presents a new approach to FPGA compilation that more closely follows the software compilation model than that of the application specific integrated circuit (ASIC). Instead of re-compiling every module in the design for each invocation of the …