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Spatial Indexing For System-Level Evaluation Of 5g Heterogeneous Cellular Networks, Roohollah Amiri, Eren Balevi, Jeffrey G. Andrews, Hani Mehrpouyan
Spatial Indexing For System-Level Evaluation Of 5g Heterogeneous Cellular Networks, Roohollah Amiri, Eren Balevi, Jeffrey G. Andrews, Hani Mehrpouyan
Electrical and Computer Engineering Faculty Publications and Presentations
System level simulations of large 5G networks are essential to evaluate and design algorithms related to network issues such as scheduling, mobility management, interference management, and cell planning. In this paper, we look back to the idea of spatial indexing and its advantages, applications, and future potentials in accelerating large 5G network simulations. We introduce a multi-level inheritance based architecture which is used to index all elements of a heterogeneous network (HetNet) on a single geometry tree. Then, we define spatial queries to accelerate searches in distance, azimuth, and elevation. We demonstrate that spatial indexing can accelerate location-based searches by …
Case Study Of Finite Resource Optimization In Fpga Using Genetic Algorithm, Jingxia Wang, Sin Ming Loo
Case Study Of Finite Resource Optimization In Fpga Using Genetic Algorithm, Jingxia Wang, Sin Ming Loo
Electrical and Computer Engineering Faculty Publications and Presentations
Modem Field-Programmable Gate Arrays (FPGAs) are becoming very popular in embedded systems and high performance applications. FPGA has benefited from the shrinking of transistor feature size, which allows more on-chip reconfigurable (e.g., memories and look-up tables) and routing resources available. Unfortunately, the amount of reconfigurable resources in a FPGA is fixed and limited. This paper investigates the mapping scheme of the applications in a FPGA by utilizing sequential processing (e.g., Altera Nios II or Xilinx Microblaze, using C programming language) and task specific hardware (using hardware description language). Genetic Algorithm is used in this study. We found that placing sequential …
Optimizing Reconfigurable Hardware Resource Usage In System-On-A-Programmable-Chip With Location-Aware Genetic Algorithm, Sin Ming Loo, Jingxia Wang
Optimizing Reconfigurable Hardware Resource Usage In System-On-A-Programmable-Chip With Location-Aware Genetic Algorithm, Sin Ming Loo, Jingxia Wang
Electrical and Computer Engineering Faculty Publications and Presentations
This paper presents static task scheduling using location-aware genetic algorithm techniques to schedule task systems to finite amounts of reconfigurable hardware. This research optimizes the use of limited reconfigurable resources. This scheduling algorithm is built upon our previous work [12- 14]. In this paper, the genetic algorithm has been expanded to include a feature to assign selected tasks to specific functional units. In this reconfigurable hardware environment, multiple sequential processing elements (soft core processors such as Xilinx MicroBlaze [22] or Altera Nios-II [1]), task-specific core (application specific hardware), and communication network within the reconfigurable hardware can be used (such a …