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Clock Partitioning For Testability, Kent L. Einspahr, Sharad C. Seth, Vishwani D. Agrawal
Clock Partitioning For Testability, Kent L. Einspahr, Sharad C. Seth, Vishwani D. Agrawal
CSE Conference and Workshop Papers
An implementation of a design for testability model for sequential circuits is presented. The flip-flops in a sequential circuit are partitioned to reduce the number of cycles and the path lengths in each partition, thereby reducing the complexity of test generation. The implementation includes a Podem-based test generator. Preliminary results using the Contest sequential test generator are presented.