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Practical Irrigation Scheduling Program, Dominic Sween
Practical Irrigation Scheduling Program, Dominic Sween
BioResource and Agricultural Engineering
This senior project discusses the design, construction, and evaluation of an irrigation scheduling program that aids users in alfalfa irrigation management, with the potential for application with other crops. The program uses a very accurate irrigation prediction model that forecasts what the estimated irrigation need of each week will be, as well as the number of irrigations needed to satisfy the requirement. The model was found to predict the sum of the actual required weekly irrigation amount within less than 1% of the true value. The program was based off the single crop coefficient approach that was outlined previously by …
Cada: Channel And Delay Aware Scheduler For Real-Time Applications In Wimax Networks, Melek Oktay, Haci Ali̇ Mantar
Cada: Channel And Delay Aware Scheduler For Real-Time Applications In Wimax Networks, Melek Oktay, Haci Ali̇ Mantar
Turkish Journal of Electrical Engineering and Computer Sciences
Scheduling is the core of the worldwide interoperability for microwave access (WiMAX) technology that directly affects the performance of the network. In this study, we focus on scheduling and present a novel algorithm called the channel and delay aware scheduler (CADA) for real-time applications, such as voice over Internet protocol, video-on-demand, and video streaming. CADA has 2 important modules: wireless and network delay monitoring tools. The wireless module, including the compensation and channel state monitoring modules, increases the network throughput and provides fairness among all of the flows in the network. The network delay monitoring tool calculates the estimated network …
Power-Efficient And Low-Latency Memory Access For Cmp Systems With Heterogeneous Scratchpad On-Chip Memory, Zhi Chen
Theses and Dissertations--Electrical and Computer Engineering
The gradually widening speed disparity of between CPU and memory has become an overwhelming bottleneck for the development of Chip Multiprocessor (CMP) systems. In addition, increasing penalties caused by frequent on-chip memory accesses have raised critical challenges in delivering high memory access performance with tight power and latency budgets. To overcome the daunting memory wall and energy wall issues, this thesis focuses on proposing a new heterogeneous scratchpad memory architecture which is configured from SRAM, MRAM, and Z-RAM. Based on this architecture, we propose two algorithms, a dynamic programming and a genetic algorithm, to perform data allocation to different memory …