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Copper Electrodeposition In Full Wafer Thickness Through-Silicon Vias, Rebecca P. Schmitt

Chemical and Biological Engineering ETDs

Through-silicon vias (TSVs) are a key interconnect technology for advanced packaging of microelectronic devices, and full wafer thickness TSVs are required for certain microelectromechanical systems (MEMS) applications. In this work, electrolytes containing copper sulfate, an acid, chloride, and Tetronic 701 suppressor were implemented for Cu filling of high aspect ratio (10:1), full wafer thickness TSVs. For each electrolyte system, rotating disk electrode voltammetry was used to identify a voltage range for bottom-up Cu filling in the TSVs. Die level feature filling was performed using voltage ramping, which moved active deposition through the vias to yield void-free Cu features. During voltage-controlled …