Digital Circuits Commons^™

Prosense, Johnny Favazza Ii, Casey Glasgow, Matt Epperson

Computer Engineering

This project aims to gather advanced data sets from MEMS sensors and GPS and deliver it to the user, who can capitalize on the data. The once negligible half-degree difference of your board barreling down a wave can be recorded from a gyro and exploited for the perfect turn. The exact speed dreaded by longboarders where speed wobbles turn into a road rash can be analysed and consequently avoided. Ascertaining the summit of your flight using combined GPS sensors from the ski ramp allows for the correct timing of tricks. When it comes to pursuing excellence in professional sports, amateur …

El Capitán: Cal Poly Rose Float Digital Drive System, Gregory Raffi Baghdikian

Computer Engineering

In today’s world of smartphones, self-driving cars, and internet-connected coffee makers, it seems as if computers are contained in everything around us. These “embedded systems” have become critical components of our lives, improving everything about the things they control, from cost, to speed, to simplicity. One area that embedded systems has hardly gained a foothold is in the world of floatbuilding. Most of the floats in the Tournament of Roses Parade, including the one built jointly by Cal Poly San Luis Obispo and Cal Poly Pomona, are technologically very simple, using mostly analog components and rudimentary discrete digital logic to …

A Low Cost Timing Generation Unit, Christopher Vochoska

Computer Engineering

No abstract provided.

Pinpoint: Location Beacon And Tracking, Ezequiel Lopez Iii

Computer Engineering

The purpose of Pinpoint was to create a device that can collect and transmit location information for multiple users on a wireless network. The device would be used to keep track of and communicate with other users nearby. The final design includes a touchscreen display as a graphical user interface (GUI), an XBee RF module for wireless networking, a GPS receiver for location tracking, and a Programmable System on a Chip (PSoC) to control the modules.

Achieving A Better Balance Between Productivity And Performance On Fpgas Through Heterogeneous Extensible Multiprocessor Systems, Abazar Sadeghian

Graduate Theses and Dissertations

Field Programmable Gate Arrays (FPGAs) were first introduced circa 1980, and they held the promise of delivering performance levels associated with customized circuits, but with productivity levels more closely associated with software development. Achieving both performance and productivity objectives has been a long standing challenge problem for the reconfigurable computing community and remains unsolved today. On one hand, Vendor supplied design flows have tended towards achieving the high levels of performance through gate level customization, but at the cost of very low productivity. On the other hand, FPGA densities are following Moore's law and and can now support complete multiprocessor …

Ac Power Monitoring System Provides Individual Circuit Energy Consumption Data, Jared L. Newman, Grayson H. Dearing, Luke M. Tomlinson, Frederick G. Harmon

The Research and Scholarship Symposium (2013-2019)

Motivated by high energy costs, people and organizations want to cut back on their energy consumption. However, the only feedback consumers typically receive is a monthly bill listing their total electricity usage (in kWh). Some companies have begun developing systems that allow households and organizations to monitor their energy usage for individual circuits. Available systems are expensive so a CU engineering senior design team has designed, fabricated, and tested a system for use at Cedarville University. The AC power monitoring system has the ability to measure energy consumption for each individual circuit in the breaker panel, store the data, and …

“My Logic Is Undeniable”: Replicating The Brain For Ideal Artificial Intelligence, Samuel C. Adams

Senior Honors Theses

Alan Turing asked if machines can think, but intelligence is more than logic and reason. I ask if a machine can feel pain or joy, have visions and dreams, or paint a masterpiece. The human brain sets the bar high, and despite our progress, artificial intelligence has a long way to go. Studying neurology from a software engineer’s perspective reveals numerous uncanny similarities between the functionality of the brain and that of a computer. If the brain is a biological computer, then it is the embodiment of artificial intelligence beyond anything we have yet achieved, and its architecture is advanced …

A High Performance Advanced Encryption Standard (Aes) Encrypted On-Chip Bus Architecture For Internet-Of-Things (Iot) System-On-Chips (Soc), Xiaokun Yang

FIU Electronic Theses and Dissertations

With industry expectations of billions of Internet-connected things, commonly referred to as the IoT, we see a growing demand for high-performance on-chip bus architectures with the following attributes: small scale, low energy, high security, and highly configurable structures for integration, verification, and performance estimation.

Our research thus mainly focuses on addressing these key problems and finding the balance among all these requirements that often work against each other. First of all, we proposed a low-cost and low-power System-on-Chips (SoCs) architecture (IBUS) that can frame data transfers differently. The IBUS protocol provides two novel transfer modes – the block and state …

System And Method For Identifying Electrical Properties Of Integrate Circuits, Mary Y. Lanzerotti

AFIT Patents

A new method for displaying electrical properties for integrated circuit (IC) layout designs provides for improved human visualization of those properties and comparison of as designed layout design parameters to as specified layout design parameters and to as manufactured layout parameters. The method starts with a circuitry as designed layout in a first digital format, extracts values for electrical properties from that circuitry as designed layout then annotates those values back into the first digital format. The annotated circuitry as designed layout is then converted from the first digital format to a second digital format that can be converted to …

How Much A Quarter Cost: Allegory Of A Coin And Other Stories, Grant C. Gallo

The Downtown Review

The philosophical theories of Baruch Spinoza and George Berkley were described, compared, and contrasted. Various examples and metaphors were used to help fully illustrate their respective metaphysical, epistemological, and ethical positions. The relevance of their theories to current philosophical discourse was discussed; showing that even in today’s technologically advanced society, seemingly antiquated ideas may still provide useful knowledge. In the end, Spinoza and Berkley’s apparently conflicting paradigms are rectified through a multiplexual, relativistic lens.

Formal Modeling And Verification Of Delay-Insensitive Circuits, Hoon Park

Dissertations and Theses

Einstein's relativity theory tells us that the notion of simultaneity can only be approximated for events distributed over space. As a result, the use of asynchronous techniques is unavoidable in systems larger than a certain physical size. Traditional design techniques that use global clocks face this barrier of scale already within the space of a modern microprocessor chip. The most common response by the chip industry for overcoming this barrier is to use Globally Asynchronous Locally Synchronous (GALS) design techniques. The circuits investigated in this thesis can be viewed as examples of GALS design. To make such designs trustworthy it …

Data And Network Optimization Effect On Web Performance, Steven Rosenberg, Surbhi Dangi, Isuru Warnakulasooriya

Surbhi Dangi

In this study, we measure the effects of two software approaches to improving data and network performance: 1. Content optimization and compression; and 2. Optimizing network protocols. We achieve content optimization and compression by means of BoostEdge by ActivNetworks and employ the SPDY network protocol by Google to lower the round trip time for HTTP transactions. Since the data and transport layers are separate, we conclude our investigation by studying the combined effect of these two techniques on web performance. Using document mean load time as the measure, we found that with and without packet loss, both BoostEdge and SPDY …

Arithmetic Logic Unit Architectures With Dynamically Defined Precision, Getao Liang

Doctoral Dissertations

Modern central processing units (CPUs) employ arithmetic logic units (ALUs) that support statically defined precisions, often adhering to industry standards. Although CPU manufacturers highly optimize their ALUs, industry standard precisions embody accuracy and performance compromises for general purpose deployment. Hence, optimizing ALU precision holds great potential for improving speed and energy efficiency. Previous research on multiple precision ALUs focused on predefined, static precisions. Little previous work addressed ALU architectures with customized, dynamically defined precision. This dissertation presents approaches for developing dynamic precision ALU architectures for both fixed-point and floating-point to enable better performance, energy efficiency, and numeric accuracy. These new …

Estimation On Gibbs Entropy For An Ensemble, Lekhya Sai Sake

Electronic Theses, Projects, and Dissertations

In this world of growing technology, any small improvement in the present scenario would create a revolution. One of the popular revolutions in the computer science field is parallel computing. A single parallel execution is not sufficient to see its non-deterministic features, as same execution with the same data at different time would end up with a different path. In order to see how non deterministic a parallel execution can extend up to, creates the need of the ensemble of executions. This project implements a program to estimate the Gibbs Entropy for an ensemble of parallel executions. The goal is …

Skybridge: A New Nanoscale 3-D Computing Framework For Future Integrated Circuits, Mostafizur Rahman

Doctoral Dissertations

Continuous scaling of CMOS has been the major catalyst in miniaturization of integrated circuits (ICs) and crucial for global socio-economic progress. However, continuing the traditional way of scaling to sub-20nm technologies is proving to be very difficult as MOSFETs are reaching their fundamental performance limits [1] and interconnection bottleneck is dominating IC operational power and performance [2]. Migrating to 3-D, as a way to advance scaling, has been elusive due to inherent customization and manufacturing requirements in CMOS architecture that are incompatible with 3-D organization. Partial attempts with die-die [3] and layer-layer [4] stacking have their own limitations [5]. We …

Threat Analysis, Countermeaures And Design Strategies For Secure Computation In Nanometer Cmos Regime, Raghavan Kumar

Doctoral Dissertations

Advancements in CMOS technologies have led to an era of Internet Of Things (IOT), where the devices have the ability to communicate with each other apart from their computational power. As more and more sensitive data is processed by embedded devices, the trend towards lightweight and efficient cryptographic primitives has gained significant momentum. Achieving a perfect security in silicon is extremely difficult, as the traditional cryptographic implementations are vulnerable to various active and passive attacks. There is also a threat in the form of "hardware Trojans" inserted into the supply chain by the untrusted third-party manufacturers for economic incentives. Apart …

Function Verification Of Combinational Arithmetic Circuits, Duo Liu

Masters Theses

Hardware design verification is the most challenging part in overall hardware design process. It is because design size and complexity are growing very fast while the requirement for performance is ever higher. Conventional simulation-based verification method cannot keep up with the rapid increase in the design size, since it is impossible to exhaustively test all input vectors of a complex design. An important part of hardware verification is combinational arithmetic circuit verification. It draws a lot of attention because flattening the design into bit-level, known as the bit-blasting problem, hinders the efficiency of many current formal techniques. The goal of …

Seizure Tracker, Zachary Reardon

Computer Engineering

The goal of this project is to make a Module that enables anyone watching a person with disabilities to record any seizure that this person has under their care. Then when the Doctor/parent receives their patient/kid they are able to download all the seizures that their patient/kid had while they were away. The Doctor/parent then has the exact time, the duration of the seizure, and the type of seizure for all the seizures that have occurred while they were away from their patient/kid. From this data it is possible that the Doctor may see some sort of patterns that enables …

Universal Uav Payload Interface, Nolan Reker, David Troy Jr, Drew Troxell

Computer Engineering

Unmanned Aerial Vehicle (UAV) technology is becoming increasingly accessible for civilian use. Both open-source and commercial-purpose UAVs can be obtained affordably or even built. However, the platforms available are very segmented in their customization to a specific application (i.e. land surveying, payload delivery). This project aims to create a Universal Payload Interface (UPI) mounted to the underside of multi-rotors or other UAVs to enable the attachment of customizable sensor payloads. These payloads allow a single UAV to be rapidly reconfigured to perform a multitude of tasks.

The Universal Payload Interface facilitates communication between the payload, onboard flight controller, and operator …

Forest Sign Maker, Victor Espinosa Iii, Kevin Ly, Lisa Yip

Mechanical Engineering

Executive Summary:

The Inyo National Forest is arguably one of the most beautiful locations in California, containing natural masterpieces such as Mount Whitney and the Ancient Bristlecone Pine Forest. Despite its magnificence, the Inyo National Forest can be a treacherous region. The Friends of the Inyo take pride in being able to facilitate the viewing experience for all outdoorsmen by maintaining the mountain trails, which includes providing adequate trail signage.

Unfortunately, there is a fundamental issue with the recent state of trail signage in the Inyo National Forest: the rate at which signs are being vandalized or naturally destroyed is …